[V8] Implement SIMD Boolean vector types to allow mask registers.

[V8] Implement SIMD Boolean vector types to allow mask registers.
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types. These are unlikely to be well supported natively,
  and can be synthesized using Select.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124
Review-Url: https://codereview.chromium.org/2700813002
Cr-Commit-Position: refs/heads/master@{#43348}
Committed: https://chromium.googlesource.com/v8/v8/+/9fe0b4c7080daf0f52aaabf91ddaf0c6632cfbf8

[bbudge, 2017-02-16 20:51:19]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-16 20:51:26]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[bbudge, 2017-02-16 21:02:11]

Description was changed from

==========
[Wasm Simd] Implement correct Boolean vector handling to prepare for AVX.
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124
==========

to

==========
[V8] Implement correct Boolean vector handling to support mask registers (AVX).
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124
==========

[bbudge, 2017-02-16 21:09:35]

Description was changed from

==========
[V8] Implement correct Boolean vector handling to support mask registers (AVX).
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124
==========

to

==========
[V8] Implement correct Boolean vector handling to support mask registers (AVX).
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types. These are unlikely to be supported natively,
  and can be synthesized using Select.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124
==========

[bbudge, 2017-02-16 22:27:53]

Description was changed from

==========
[V8] Implement correct Boolean vector handling to support mask registers (AVX).
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types. These are unlikely to be supported natively,
  and can be synthesized using Select.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124
==========

to

==========
[V8] Implement SIMD Boolean vector types to allow mask registers.
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types. These are unlikely to be well supported
natively,
  and can be synthesized using Select.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124
==========

[bbudge, 2017-02-16 22:28:20]

bbudge@chromium.org changed reviewers:
+ bmeurer@chromium.org, bradnelson@chromium.org

[bbudge, 2017-02-16 22:28:28]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-16 22:32:21]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-02-16 22:55:45]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-16 22:55:46]

Dry run: This issue passed the CQ dry run.

[bradnelson, 2017-02-16 23:18:31]

lgtm, but wait for bmeurer too.

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/function-body-...
File src/wasm/function-body-decoder-impl.h (right):

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/function-body-...
src/wasm/function-body-decoder-impl.h:148: *result = kWasmS4;
Maybe S1x4 for consistency?

Would using SB4/8/16 be better? Not sure.

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/wasm-opcodes.h
File src/wasm/wasm-opcodes.h (right):

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/wasm-opcodes.h...
src/wasm/wasm-opcodes.h:298: V(F32x4Ne, 0xe511, s4_ss)              \
Maybe b4 or sb4
Maybe...

[gdeepti, 2017-02-17 17:51:47]

gdeepti@chromium.org changed reviewers:
+ gdeepti@chromium.org

[gdeepti, 2017-02-17 17:51:48]

https://codereview.chromium.org/2700813002/diff/40001/src/compiler/arm/code-g...
File src/compiler/arm/code-generator-arm.cc (right):

https://codereview.chromium.org/2700813002/diff/40001/src/compiler/arm/code-g...
src/compiler/arm/code-generator-arm.cc:1931: __ Move(i.OutputSimd128Register(),
i.InputSimd128Register(0));
Would it be possible to use DefineSameAsFirst in the instruction selector with a
different Visit method to  remove the Move instruction here? Same comment for
the two Select opcodes below.

[Benedikt Meurer, 2017-02-17 19:14:28]

LGTM from my side.

[bbudge, 2017-02-17 22:56:08]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-17 22:56:14]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-02-17 23:25:30]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-17 23:25:31]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-02-17 23:39:35]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-17 23:39:38]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[bbudge, 2017-02-17 23:39:56]

https://codereview.chromium.org/2700813002/diff/40001/src/compiler/arm/code-g...
File src/compiler/arm/code-generator-arm.cc (right):

https://codereview.chromium.org/2700813002/diff/40001/src/compiler/arm/code-g...
src/compiler/arm/code-generator-arm.cc:1931: __ Move(i.OutputSimd128Register(),
i.InputSimd128Register(0));
On 2017/02/17 17:51:48, gdeepti wrote:
> Would it be possible to use DefineSameAsFirst in the instruction selector with
a
> different Visit method to  remove the Move instruction here? Same comment for
> the two Select opcodes below. 

Yes, that seems better. Also, I noticed that these ops are now identical for all
SIMD formats, so I merged them into a single case.

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/function-body-...
File src/wasm/function-body-decoder-impl.h (right):

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/function-body-...
src/wasm/function-body-decoder-impl.h:148: *result = kWasmS4;
On 2017/02/16 23:18:30, bradnelson wrote:
> Maybe S1x4 for consistency?
> 
> Would using SB4/8/16 be better? Not sure.

I like S1xN. I'm also going to change the MachineTypes kSimdBoolN to kSimd1xN to
match.

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/wasm-opcodes.h
File src/wasm/wasm-opcodes.h (right):

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/wasm-opcodes.h...
src/wasm/wasm-opcodes.h:25: kLocalS4 = 0x7a,
Changed these to kLocalS1xN to match MachineType.

https://codereview.chromium.org/2700813002/diff/40001/src/wasm/wasm-opcodes.h...
src/wasm/wasm-opcodes.h:298: V(F32x4Ne, 0xe511, s4_ss)              \
On 2017/02/16 23:18:30, bradnelson wrote:
> Maybe b4 or sb4
> Maybe...

Changing sN to s1xN to match other renamings. Using 's' is good to emphasize
that it's SIMD, and the shape (1xN) emphasizes that a specific type is required.

[bbudge, 2017-02-17 23:41:09]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-17 23:41:18]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[bbudge, 2017-02-18 00:18:49]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-18 00:18:53]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[gdeepti, 2017-02-18 00:27:32]

lgtm

[commit-bot: I haz the power, 2017-02-18 00:47:52]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-18 00:47:53]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-02-21 15:59:38]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-21 15:59:42]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-02-21 16:40:45]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-21 16:40:47]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-02-21 16:43:14]

The CQ bit was checked by bbudge@chromium.org

[bbudge, 2017-02-21 16:43:15]

The patchset sent to the CQ was uploaded after l-g-t-m from
bmeurer@chromium.org, bradnelson@chromium.org, gdeepti@chromium.org
Link to the patchset: https://codereview.chromium.org/2700813002/#ps120001
(title: "Rebase.")

[commit-bot: I haz the power, 2017-02-21 16:43:24]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-02-21 16:45:31]

CQ is committing da patch.

Bot data: {"patchset_id": 120001, "attempt_start_ts": 1487695394888100,
"parent_rev": "fd596007f23a6f33b5d71b76a977400336f55d5a", "commit_rev":
"9fe0b4c7080daf0f52aaabf91ddaf0c6632cfbf8"}

[commit-bot: I haz the power, 2017-02-21 16:45:35]

Description was changed from

==========
[V8] Implement SIMD Boolean vector types to allow mask registers.
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types. These are unlikely to be well supported
natively,
  and can be synthesized using Select.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124
==========

to

==========
[V8] Implement SIMD Boolean vector types to allow mask registers.
- Adds new machine types SimdBool4/8/16 for the different boolean vector types.
- Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
- Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
  opcodes from the Boolean types. These are unlikely to be well supported
natively,
  and can be synthesized using Select.
- Changes the signature of Relational opcodes to return boolean vectors.
- Changes the signature of Select opcodes to take boolean vectors.
- Updates the ARM implementation of Relational and Select opcodes.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2700813002
Cr-Commit-Position: refs/heads/master@{#43348}
Committed:
https://chromium.googlesource.com/v8/v8/+/9fe0b4c7080daf0f52aaabf91ddaf0c6632...
==========

[commit-bot: I haz the power, 2017-02-21 16:45:36]

Committed patchset #7 (id:120001) as
https://chromium.googlesource.com/v8/v8/+/9fe0b4c7080daf0f52aaabf91ddaf0c6632...