[V8] Implement SIMD Boolean vector types to allow mask registers.

src/compiler/arm/code-generator-arm.cc

Index: src/compiler/arm/code-generator-arm.cc
diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
index ca0174569dd662bd3af7853357b2401b5e8f593f..80c486c472c51268dd51ccfd18f09e61e92d4ded 100644
--- a/src/compiler/arm/code-generator-arm.cc
+++ b/src/compiler/arm/code-generator-arm.cc
@@ -1926,26 +1926,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vmvn(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
-    case kArmSimd32x4Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
-      __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
-              i.InputSimd128Register(2));
-      break;
-    }
-    case kArmSimd16x8Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
-      __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
-              i.InputSimd128Register(2));
-      break;
-    }
+    case kArmSimd32x4Select:
+    case kArmSimd16x8Select:
     case kArmSimd8x16Select: {
-      // Canonicalize input 0 lanes to all 0's or all 1's and move to dest.
-      __ vtst(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
-              i.InputSimd128Register(0));
+      // vbsl clobbers the mask input so make sure it was DefineSameAsFirst.
+      DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0)));
       __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
               i.InputSimd128Register(2));
       break;