Subzero: Make the register allocator more robust with -reg-use and -reg-exclude.

Subzero: Make the register allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can get failures because of inherently high register pressure, and there are also contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local register availability optimization, and the div instruction, you can end up needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for each register class, and allow the register allocator to draw from that as a last resort.  This behavior is guarded by the -reg-reserve flag.

This CL also includes two improvements in lowering sequences to reduce register pressure.

BUG= none
R=kschimpf@google.com

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=b40595a17b83cca5d11f8d056a4ac5a4d8102a84

[Jim Stichnoth, 2016-01-28 00:18:21]

Description was changed from

==========
Subzero: Make the registoc allocator more robust with -reg-use and -reg-exclude.

BUG= none
==========

to

==========
Subzero: Make the registoc allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.

BUG= none
==========

[Jim Stichnoth, 2016-01-28 00:40:04]

Description was changed from

==========
Subzero: Make the registoc allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.

BUG= none
==========

to

==========
Subzero: Make the registoc allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.  This behavior is guarded by the -reg-reserve flag.

This CL also includes two improvements in lowering sequences to reduce register
pressure.

BUG= none
==========

[Jim Stichnoth, 2016-01-28 00:48:52]

stichnot@chromium.org changed reviewers:
+ eholk@chromium.org, jpp@chromium.org, kschimpf@google.com, sehr@chromium.org

[Jim Stichnoth, 2016-01-28 00:50:02]

This enhancement could use better diagnostics to help find more places where
register pressure could be reduced, but I would save that for another CL.

[Jim Stichnoth, 2016-01-28 17:47:33]

Description was changed from

==========
Subzero: Make the registoc allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.  This behavior is guarded by the -reg-reserve flag.

This CL also includes two improvements in lowering sequences to reduce register
pressure.

BUG= none
==========

to

==========
Subzero: Make the registor allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.  This behavior is guarded by the -reg-reserve flag.

This CL also includes two improvements in lowering sequences to reduce register
pressure.

BUG= none
==========

[Jim Stichnoth, 2016-01-28 17:47:50]

Description was changed from

==========
Subzero: Make the registor allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.  This behavior is guarded by the -reg-reserve flag.

This CL also includes two improvements in lowering sequences to reduce register
pressure.

BUG= none
==========

to

==========
Subzero: Make the register allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.  This behavior is guarded by the -reg-reserve flag.

This CL also includes two improvements in lowering sequences to reduce register
pressure.

BUG= none
==========

[Karl, 2016-01-28 21:10:56]

LGTM. Register allocation code looks ok, but I don't know enough to be sure.

[Jim Stichnoth, 2016-01-29 14:14:35]

Description was changed from

==========
Subzero: Make the register allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.  This behavior is guarded by the -reg-reserve flag.

This CL also includes two improvements in lowering sequences to reduce register
pressure.

BUG= none
==========

to

==========
Subzero: Make the register allocator more robust with -reg-use and -reg-exclude.

The problem is that if you too aggressively -reg-use or -reg-exclude, you can
get failures because of inherently high register pressure, and there are also
contributions from the "specialty" register classes.

For example, when you combine load optimization, address mode inference, local
register availability optimization, and the div instruction, you can end up
needing 5 simultaneously live infinite-weight registers.

The fix/enhancement here is to keep track of the "reserve" set of registers for
each register class, and allow the register allocator to draw from that as a
last resort.  This behavior is guarded by the -reg-reserve flag.

This CL also includes two improvements in lowering sequences to reduce register
pressure.

BUG= none
R=kschimpf@google.com

Committed:
https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a...
==========

[Jim Stichnoth, 2016-01-29 14:14:37]

Committed patchset #2 (id:20001) manually as
b40595a17b83cca5d11f8d056a4ac5a4d8102a84 (presubmit successful).