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| 1 //===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 268 RegSet_CallerSave = 1 << 0, | 268 RegSet_CallerSave = 1 << 0, |
| 269 RegSet_CalleeSave = 1 << 1, | 269 RegSet_CalleeSave = 1 << 1, |
| 270 RegSet_StackPointer = 1 << 2, | 270 RegSet_StackPointer = 1 << 2, |
| 271 RegSet_FramePointer = 1 << 3, | 271 RegSet_FramePointer = 1 << 3, |
| 272 RegSet_All = ~RegSet_None | 272 RegSet_All = ~RegSet_None |
| 273 }; | 273 }; |
| 274 using RegSetMask = uint32_t; | 274 using RegSetMask = uint32_t; |
| 275 | 275 |
| 276 virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 276 virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
| 277 RegSetMask Exclude) const = 0; | 277 RegSetMask Exclude) const = 0; |
| 278 /// Get the set of physical registers available for the specified Variable's |
| 279 /// register class, applying register restrictions from the command line. |
| 278 virtual const llvm::SmallBitVector & | 280 virtual const llvm::SmallBitVector & |
| 279 getRegistersForVariable(const Variable *Var) const = 0; | 281 getRegistersForVariable(const Variable *Var) const = 0; |
| 282 /// Get the set of *all* physical registers available for the specified |
| 283 /// Variable's register class, *not* applying register restrictions from the |
| 284 /// command line. |
| 285 virtual const llvm::SmallBitVector & |
| 286 getAllRegistersForVariable(const Variable *Var) const = 0; |
| 280 virtual const llvm::SmallBitVector &getAliasesForRegister(SizeT) const = 0; | 287 virtual const llvm::SmallBitVector &getAliasesForRegister(SizeT) const = 0; |
| 281 | 288 |
| 282 void regAlloc(RegAllocKind Kind); | 289 void regAlloc(RegAllocKind Kind); |
| 283 | 290 |
| 284 virtual void | 291 virtual void |
| 285 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, | 292 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, |
| 286 const llvm::SmallBitVector &ExcludeRegisters, | 293 const llvm::SmallBitVector &ExcludeRegisters, |
| 287 uint64_t Salt) const = 0; | 294 uint64_t Salt) const = 0; |
| 288 | 295 |
| 289 /// Get the minimum number of clusters required for a jump table to be | 296 /// Get the minimum number of clusters required for a jump table to be |
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| 561 virtual void lower() {} | 568 virtual void lower() {} |
| 562 | 569 |
| 563 protected: | 570 protected: |
| 564 explicit TargetHeaderLowering(GlobalContext *Ctx) : Ctx(Ctx) {} | 571 explicit TargetHeaderLowering(GlobalContext *Ctx) : Ctx(Ctx) {} |
| 565 GlobalContext *Ctx; | 572 GlobalContext *Ctx; |
| 566 }; | 573 }; |
| 567 | 574 |
| 568 } // end of namespace Ice | 575 } // end of namespace Ice |
| 569 | 576 |
| 570 #endif // SUBZERO_SRC_ICETARGETLOWERING_H | 577 #endif // SUBZERO_SRC_ICETARGETLOWERING_H |
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