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Side by Side Diff: src/IceTargetLoweringX8664.cpp

Issue 1641653004: Subzero: Make the register allocator more robust with -reg-use and -reg-exclude. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Test code accidentally left in Created 4 years, 10 months ago
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1 //===- subzero/src/IceTargetLoweringX8664.cpp - x86-64 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8664.cpp - x86-64 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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100 llvm::array_lengthof(TableTypeX8664Attributes); 100 llvm::array_lengthof(TableTypeX8664Attributes);
101 101
102 const uint32_t TargetX8664Traits::X86_STACK_ALIGNMENT_BYTES = 16; 102 const uint32_t TargetX8664Traits::X86_STACK_ALIGNMENT_BYTES = 16;
103 const char *TargetX8664Traits::TargetName = "X8664"; 103 const char *TargetX8664Traits::TargetName = "X8664";
104 104
105 template <> 105 template <>
106 std::array<llvm::SmallBitVector, RCX86_NUM> 106 std::array<llvm::SmallBitVector, RCX86_NUM>
107 TargetX86Base<X8664::Traits>::TypeToRegisterSet = {{}}; 107 TargetX86Base<X8664::Traits>::TypeToRegisterSet = {{}};
108 108
109 template <> 109 template <>
110 std::array<llvm::SmallBitVector, RCX86_NUM>
111 TargetX86Base<X8664::Traits>::TypeToRegisterSetUnfiltered = {{}};
112
113 template <>
110 std::array<llvm::SmallBitVector, 114 std::array<llvm::SmallBitVector,
111 TargetX86Base<X8664::Traits>::Traits::RegisterSet::Reg_NUM> 115 TargetX86Base<X8664::Traits>::Traits::RegisterSet::Reg_NUM>
112 TargetX86Base<X8664::Traits>::RegisterAliases = {{}}; 116 TargetX86Base<X8664::Traits>::RegisterAliases = {{}};
113 117
114 template <> 118 template <>
115 FixupKind TargetX86Base<X8664::Traits>::PcRelFixup = 119 FixupKind TargetX86Base<X8664::Traits>::PcRelFixup =
116 TargetX86Base<X8664::Traits>::Traits::FK_PcRel; 120 TargetX86Base<X8664::Traits>::Traits::FK_PcRel;
117 121
118 template <> 122 template <>
119 FixupKind TargetX86Base<X8664::Traits>::AbsFixup = 123 FixupKind TargetX86Base<X8664::Traits>::AbsFixup =
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774 #define X(tag, sizeLog2, align, elts, elty, str, rcstr) \ 778 #define X(tag, sizeLog2, align, elts, elty, str, rcstr) \
775 static_assert(_table1_##tag == _table2_##tag, \ 779 static_assert(_table1_##tag == _table2_##tag, \
776 "Inconsistency between ICETYPEX8664_TABLE and ICETYPE_TABLE"); 780 "Inconsistency between ICETYPEX8664_TABLE and ICETYPE_TABLE");
777 ICETYPE_TABLE 781 ICETYPE_TABLE
778 #undef X 782 #undef X
779 } // end of namespace dummy3 783 } // end of namespace dummy3
780 } // end of anonymous namespace 784 } // end of anonymous namespace
781 785
782 } // end of namespace X8664 786 } // end of namespace X8664
783 } // end of namespace Ice 787 } // end of namespace Ice
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