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Side by Side Diff: src/IceTargetLoweringARM32.cpp

Issue 1641653004: Subzero: Make the register allocator more robust with -reg-use and -reg-exclude. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Test code accidentally left in Created 4 years, 10 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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335 TypeToRegisterSet[IceType_f32] = Float32Registers; 335 TypeToRegisterSet[IceType_f32] = Float32Registers;
336 TypeToRegisterSet[IceType_f64] = Float64Registers; 336 TypeToRegisterSet[IceType_f64] = Float64Registers;
337 TypeToRegisterSet[IceType_v4i1] = VectorRegisters; 337 TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
338 TypeToRegisterSet[IceType_v8i1] = VectorRegisters; 338 TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
339 TypeToRegisterSet[IceType_v16i1] = VectorRegisters; 339 TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
340 TypeToRegisterSet[IceType_v16i8] = VectorRegisters; 340 TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
341 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; 341 TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
342 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; 342 TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
343 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; 343 TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
344 344
345 for (size_t i = 0; i < llvm::array_lengthof(TypeToRegisterSet); ++i)
346 TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i];
347
345 filterTypeToRegisterSet( 348 filterTypeToRegisterSet(
346 Ctx, RegARM32::Reg_NUM, TypeToRegisterSet, 349 Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
347 llvm::array_lengthof(TypeToRegisterSet), [](int32_t RegNum) -> IceString { 350 llvm::array_lengthof(TypeToRegisterSet), [](int32_t RegNum) -> IceString {
348 // This function simply removes ", " from the register name. 351 // This function simply removes ", " from the register name.
349 IceString Name = RegARM32::getRegName(RegNum); 352 IceString Name = RegARM32::getRegName(RegNum);
350 constexpr const char RegSeparator[] = ", "; 353 constexpr const char RegSeparator[] = ", ";
351 constexpr size_t RegSeparatorWidth = 354 constexpr size_t RegSeparatorWidth =
352 llvm::array_lengthof(RegSeparator) - 1; 355 llvm::array_lengthof(RegSeparator) - 1;
353 for (size_t Pos = Name.find(RegSeparator); Pos != std::string::npos; 356 for (size_t Pos = Name.find(RegSeparator); Pos != std::string::npos;
354 Pos = Name.find(RegSeparator)) { 357 Pos = Name.find(RegSeparator)) {
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6495 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n"; 6498 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n";
6496 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) { 6499 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
6497 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n"; 6500 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n";
6498 } 6501 }
6499 // Technically R9 is used for TLS with Sandboxing, and we reserve it. 6502 // Technically R9 is used for TLS with Sandboxing, and we reserve it.
6500 // However, for compatibility with current NaCl LLVM, don't claim that. 6503 // However, for compatibility with current NaCl LLVM, don't claim that.
6501 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; 6504 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n";
6502 } 6505 }
6503 6506
6504 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; 6507 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
6508 llvm::SmallBitVector
6509 TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
6505 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; 6510 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
6506 6511
6507 } // end of namespace ARM32 6512 } // end of namespace ARM32
6508 } // end of namespace Ice 6513 } // end of namespace Ice
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