| OLD | NEW |
| 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 98 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 109 TypeToRegisterSet[IceType_f32] = Float32Registers; | 109 TypeToRegisterSet[IceType_f32] = Float32Registers; |
| 110 TypeToRegisterSet[IceType_f64] = Float64Registers; | 110 TypeToRegisterSet[IceType_f64] = Float64Registers; |
| 111 TypeToRegisterSet[IceType_v4i1] = VectorRegisters; | 111 TypeToRegisterSet[IceType_v4i1] = VectorRegisters; |
| 112 TypeToRegisterSet[IceType_v8i1] = VectorRegisters; | 112 TypeToRegisterSet[IceType_v8i1] = VectorRegisters; |
| 113 TypeToRegisterSet[IceType_v16i1] = VectorRegisters; | 113 TypeToRegisterSet[IceType_v16i1] = VectorRegisters; |
| 114 TypeToRegisterSet[IceType_v16i8] = VectorRegisters; | 114 TypeToRegisterSet[IceType_v16i8] = VectorRegisters; |
| 115 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; | 115 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; |
| 116 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; | 116 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; |
| 117 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; | 117 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; |
| 118 | 118 |
| 119 for (size_t i = 0; i < llvm::array_lengthof(TypeToRegisterSet); ++i) |
| 120 TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i]; |
| 121 |
| 119 filterTypeToRegisterSet(Ctx, RegMIPS32::Reg_NUM, TypeToRegisterSet, | 122 filterTypeToRegisterSet(Ctx, RegMIPS32::Reg_NUM, TypeToRegisterSet, |
| 120 llvm::array_lengthof(TypeToRegisterSet), | 123 llvm::array_lengthof(TypeToRegisterSet), |
| 121 RegMIPS32::getRegName, getRegClassName); | 124 RegMIPS32::getRegName, getRegClassName); |
| 122 } | 125 } |
| 123 | 126 |
| 124 void TargetMIPS32::translateO2() { | 127 void TargetMIPS32::translateO2() { |
| 125 TimerMarker T(TimerStack::TT_O2, Func); | 128 TimerMarker T(TimerStack::TT_O2, Func); |
| 126 | 129 |
| 127 // TODO(stichnot): share passes with X86? | 130 // TODO(stichnot): share passes with X86? |
| 128 // https://code.google.com/p/nativeclient/issues/detail?id=4094 | 131 // https://code.google.com/p/nativeclient/issues/detail?id=4094 |
| (...skipping 990 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1119 void TargetHeaderMIPS32::lower() { | 1122 void TargetHeaderMIPS32::lower() { |
| 1120 OstreamLocker L(Ctx); | 1123 OstreamLocker L(Ctx); |
| 1121 Ostream &Str = Ctx->getStrEmit(); | 1124 Ostream &Str = Ctx->getStrEmit(); |
| 1122 Str << "\t.set\t" | 1125 Str << "\t.set\t" |
| 1123 << "nomicromips\n"; | 1126 << "nomicromips\n"; |
| 1124 Str << "\t.set\t" | 1127 Str << "\t.set\t" |
| 1125 << "nomips16\n"; | 1128 << "nomips16\n"; |
| 1126 } | 1129 } |
| 1127 | 1130 |
| 1128 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 1131 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
| 1132 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
| 1129 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 1133 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
| 1130 | 1134 |
| 1131 } // end of namespace MIPS32 | 1135 } // end of namespace MIPS32 |
| 1132 } // end of namespace Ice | 1136 } // end of namespace Ice |
| OLD | NEW |