MIPS[64]: Support for some SIMD operations (8)

MIPS[64]: Support for some SIMD operations (8)

Add support for S1x4And, S1x4Or, S1x4Xor, S1x4Not, S1x4AnyTrue,
S1x4AllTrue, S1x8And, S1x8Or, S1x8Xor, S1x8Not, S1x8AnyTrue,
S1x8AllTrue, S1x16And, S1x16Or, S1x16Xor, S1x16Not, S1x16AnyTrue,
S1x16AllTrue, SimdLoad, SimdStore operations for mips32 and mips64
architectures.

BUG=

Review-Url: https://codereview.chromium.org/2801683003
Cr-Commit-Position: refs/heads/master@{#45662}
Committed: https://chromium.googlesource.com/v8/v8/+/3e3dbdf3e56583a0bc2d6d372b384bf7f31f29b3

[dusan.simicic, 2017-04-05 12:19:48]

dusan.simicic@imgtec.com changed reviewers:
+ bbudge@chromium.org, ivica.bogosavljevic@imgtec.com, mtrofin@chromium.org

[dusan.simicic, 2017-04-05 12:19:48]

PTAL

[bbudge, 2017-04-05 17:28:00]

lgtm

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
File src/compiler/mips/code-generator-mips.cc (right):

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1709: __ li(dst, -1);
This surprised me before I remembered the MIPS delay slot.

[dusan.simicic, 2017-04-06 10:50:11]

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
File src/compiler/mips/code-generator-mips.cc (right):

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1709: __ li(dst, -1);
On 2017/04/05 17:28:00, bbudge wrote:
> This surprised me before I remembered the MIPS delay slot.

Yes, first li() is in branch delay slot. I'll add a comment to make this a
little bit clear. Also, this works only if li() macro generates only one
instruction (imm const is small enough for 16bit offset's field).

[ivica.bogosavljevic, 2017-05-15 14:59:07]

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
File src/compiler/mips/code-generator-mips.cc (right):

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1707: __
bz_v(i.InputSimd128Register(0), &all_false);
you should not use bz_v like this. Instead you should create BranchSimd macro
the same way there is Branch macro and BranchF macro. Having in mind that delay
slots are slowly going away, this will make things easier to maintain in the
future.

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1717: __
bnz_w(i.InputSimd128Register(0), &all_true);
Same as above

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips64/code-ge...
File src/compiler/mips64/code-generator-mips64.cc (right):

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips64/code-ge...
src/compiler/mips64/code-generator-mips64.cc:2037: __
bz_v(i.InputSimd128Register(0), &all_false);
BranchSimd macro instruction

https://codereview.chromium.org/2801683003/diff/1/test/cctest/test-disasm-mip...
File test/cctest/test-disasm-mips.cc (right):

https://codereview.chromium.org/2801683003/diff/1/test/cctest/test-disasm-mip...
test/cctest/test-disasm-mips.cc:1134: COMPARE_MSA_BRANCH(bnz_v(w0, (int16_t)0),
"45e00000       bnz.v  w0, 0", 0);
use static_cast<int16_t> like the others

https://codereview.chromium.org/2801683003/diff/1/test/cctest/test-disasm-mip...
File test/cctest/test-disasm-mips64.cc (right):

https://codereview.chromium.org/2801683003/diff/1/test/cctest/test-disasm-mip...
test/cctest/test-disasm-mips64.cc:1320: COMPARE_MSA_BRANCH(bnz_v(w0,
(int16_t)0), "45e00000       bnz.v  w0, 0", 0);
static_cast<int16_t>

[dusan.simicic, 2017-05-19 08:55:02]

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
File src/compiler/mips/code-generator-mips.cc (right):

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1707: __
bz_v(i.InputSimd128Register(0), &all_false);
On 2017/05/15 14:59:06, ivica.bogosavljevic wrote:
> you should not use bz_v like this. Instead you should create BranchSimd macro
> the same way there is Branch macro and BranchF macro. Having in mind that
delay
> slots are slowly going away, this will make things easier to maintain in the
> future.

Done.

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1717: __
bnz_w(i.InputSimd128Register(0), &all_true);
On 2017/05/15 14:59:06, ivica.bogosavljevic wrote:
> Same as above

Done.

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips64/code-ge...
File src/compiler/mips64/code-generator-mips64.cc (right):

https://codereview.chromium.org/2801683003/diff/1/src/compiler/mips64/code-ge...
src/compiler/mips64/code-generator-mips64.cc:2037: __
bz_v(i.InputSimd128Register(0), &all_false);
On 2017/05/15 14:59:06, ivica.bogosavljevic wrote:
> BranchSimd macro instruction

Done.

https://codereview.chromium.org/2801683003/diff/1/test/cctest/test-disasm-mip...
File test/cctest/test-disasm-mips.cc (right):

https://codereview.chromium.org/2801683003/diff/1/test/cctest/test-disasm-mip...
test/cctest/test-disasm-mips.cc:1134: COMPARE_MSA_BRANCH(bnz_v(w0, (int16_t)0),
"45e00000       bnz.v  w0, 0", 0);
On 2017/05/15 14:59:06, ivica.bogosavljevic wrote:
> use static_cast<int16_t> like the others

Done.

https://codereview.chromium.org/2801683003/diff/1/test/cctest/test-disasm-mip...
File test/cctest/test-disasm-mips64.cc (right):

https://codereview.chromium.org/2801683003/diff/1/test/cctest/test-disasm-mip...
test/cctest/test-disasm-mips64.cc:1320: COMPARE_MSA_BRANCH(bnz_v(w0,
(int16_t)0), "45e00000       bnz.v  w0, 0", 0);
On 2017/05/15 14:59:06, ivica.bogosavljevic wrote:
> static_cast<int16_t>

Done.

[ivica.bogosavljevic, 2017-05-19 12:53:46]

mips part lgtm

[dusan.simicic, 2017-05-25 12:31:38]

dusan.simicic@imgtec.com changed reviewers:
+ bmeurer@chromium.org, jarin@chromium.org, tebbi@google.com

[dusan.simicic, 2017-05-25 12:31:39]

+ jarin, +tebbi, +bmeurer for instruction-selector.cc and test-run-wasm-simd.cc
PTAL

[dusan.simicic, 2017-05-31 09:41:32]

ping
Need lgtm from owners.

[Jarin, 2017-05-31 12:07:22]

lgtm

[dusan.simicic, 2017-05-31 13:08:10]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2017-05-31 13:08:13]

Dry run: CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-31 13:54:31]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-05-31 13:54:32]

Dry run: This issue passed the CQ dry run.

[dusan.simicic, 2017-05-31 14:35:26]

The CQ bit was checked by dusan.simicic@imgtec.com

[dusan.simicic, 2017-05-31 14:35:26]

The patchset sent to the CQ was uploaded after l-g-t-m from bbudge@chromium.org,
ivica.bogosavljevic@imgtec.com
Link to the patchset: https://codereview.chromium.org/2801683003/#ps40001
(title: "Rebase")

[commit-bot: I haz the power, 2017-05-31 14:35:34]

CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-05-31 14:38:14]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-05-31 14:38:15]

Try jobs failed on following builders:
  v8_presubmit on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_presubmit/builds/42179)

[dusan.simicic, 2017-06-01 12:28:25]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2017-06-01 12:28:30]

Dry run: CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-06-01 12:59:01]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-06-01 12:59:02]

Dry run: This issue passed the CQ dry run.

[dusan.simicic, 2017-06-01 13:24:21]

The CQ bit was checked by dusan.simicic@imgtec.com

[dusan.simicic, 2017-06-01 13:24:22]

The patchset sent to the CQ was uploaded after l-g-t-m from
ivica.bogosavljevic@imgtec.com, bbudge@chromium.org, jarin@chromium.org
Link to the patchset: https://codereview.chromium.org/2801683003/#ps60001
(title: "Rebase")

[commit-bot: I haz the power, 2017-06-01 13:24:25]

CQ is trying da patch.

Follow status at:
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-06-01 13:25:51]

CQ is committing da patch.

Bot data: {"patchset_id": 60001, "attempt_start_ts": 1496323461970240,
"parent_rev": "6a99238b9004c8e14b7f86734ef071eac8198212", "commit_rev":
"3e3dbdf3e56583a0bc2d6d372b384bf7f31f29b3"}

[commit-bot: I haz the power, 2017-06-01 13:25:58]

Description was changed from

==========
MIPS[64]: Support for some SIMD operations (8)

Add support for S1x4And, S1x4Or, S1x4Xor, S1x4Not, S1x4AnyTrue,
S1x4AllTrue, S1x8And, S1x8Or, S1x8Xor, S1x8Not, S1x8AnyTrue,
S1x8AllTrue, S1x16And, S1x16Or, S1x16Xor, S1x16Not, S1x16AnyTrue,
S1x16AllTrue, SimdLoad, SimdStore operations for mips32 and mips64
architectures.

BUG=
==========

to

==========
MIPS[64]: Support for some SIMD operations (8)

Add support for S1x4And, S1x4Or, S1x4Xor, S1x4Not, S1x4AnyTrue,
S1x4AllTrue, S1x8And, S1x8Or, S1x8Xor, S1x8Not, S1x8AnyTrue,
S1x8AllTrue, S1x16And, S1x16Or, S1x16Xor, S1x16Not, S1x16AnyTrue,
S1x16AllTrue, SimdLoad, SimdStore operations for mips32 and mips64
architectures.

BUG=

Review-Url: https://codereview.chromium.org/2801683003
Cr-Commit-Position: refs/heads/master@{#45662}
Committed:
https://chromium.googlesource.com/v8/v8/+/3e3dbdf3e56583a0bc2d6d372b384bf7f31...
==========

[commit-bot: I haz the power, 2017-06-01 13:25:59]

Committed patchset #4 (id:60001) as
https://chromium.googlesource.com/v8/v8/+/3e3dbdf3e56583a0bc2d6d372b384bf7f31...