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Side by Side Diff: src/compiler/mips/code-generator-mips.cc

Issue 2801683003: MIPS[64]: Support for some SIMD operations (8) (Closed)
Patch Set: Created 3 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/code-generator.h" 5 #include "src/compiler/code-generator.h"
6 #include "src/compilation-info.h" 6 #include "src/compilation-info.h"
7 #include "src/compiler/code-generator-impl.h" 7 #include "src/compiler/code-generator-impl.h"
8 #include "src/compiler/gap-resolver.h" 8 #include "src/compiler/gap-resolver.h"
9 #include "src/compiler/node-matchers.h" 9 #include "src/compiler/node-matchers.h"
10 #include "src/compiler/osr.h" 10 #include "src/compiler/osr.h"
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1667 case kMipsF32x4SConvertI32x4: { 1667 case kMipsF32x4SConvertI32x4: {
1668 CpuFeatureScope msa_scope(masm(), MIPS_SIMD); 1668 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1669 __ ffint_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0)); 1669 __ ffint_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
1670 break; 1670 break;
1671 } 1671 }
1672 case kMipsF32x4UConvertI32x4: { 1672 case kMipsF32x4UConvertI32x4: {
1673 CpuFeatureScope msa_scope(masm(), MIPS_SIMD); 1673 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1674 __ ffint_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0)); 1674 __ ffint_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
1675 break; 1675 break;
1676 } 1676 }
1677 case kMipsS128And: {
1678 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1679 __ and_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
1680 i.InputSimd128Register(1));
1681 break;
1682 }
1683 case kMipsS128Or: {
1684 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1685 __ or_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
1686 i.InputSimd128Register(1));
1687 break;
1688 }
1689 case kMipsS128Xor: {
1690 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1691 __ xor_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
1692 i.InputSimd128Register(1));
1693 break;
1694 }
1695 case kMipsS128Not: {
1696 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1697 __ nor_v(i.OutputSimd128Register(), i.InputSimd128Register(0),
1698 i.InputSimd128Register(0));
1699 break;
1700 }
1701 case kMipsS1x4AnyTrue:
1702 case kMipsS1x8AnyTrue:
1703 case kMipsS1x16AnyTrue: {
1704 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1705 Register dst = i.OutputRegister();
1706 Label all_false;
1707 __ bz_v(i.InputSimd128Register(0), &all_false);
ivica.bogosavljevic 2017/05/15 14:59:06 you should not use bz_v like this. Instead you sho
dusan.simicic 2017/05/19 08:55:01 Done.
1708 __ li(dst, 0);
1709 __ li(dst, -1);
bbudge 2017/04/05 17:28:00 This surprised me before I remembered the MIPS del
dusan.simicic 2017/04/06 10:50:11 Yes, first li() is in branch delay slot. I'll add
1710 __ bind(&all_false);
1711 break;
1712 }
1713 case kMipsS1x4AllTrue: {
1714 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1715 Register dst = i.OutputRegister();
1716 Label all_true;
1717 __ bnz_w(i.InputSimd128Register(0), &all_true);
ivica.bogosavljevic 2017/05/15 14:59:06 Same as above
dusan.simicic 2017/05/19 08:55:01 Done.
1718 __ li(dst, -1);
1719 __ li(dst, 0);
1720 __ bind(&all_true);
1721 break;
1722 }
1723 case kMipsS1x8AllTrue: {
1724 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1725 Register dst = i.OutputRegister();
1726 Label all_true;
1727 __ bnz_h(i.InputSimd128Register(0), &all_true);
1728 __ li(dst, -1);
1729 __ li(dst, 0);
1730 __ bind(&all_true);
1731 break;
1732 }
1733 case kMipsS1x16AllTrue: {
1734 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1735 Register dst = i.OutputRegister();
1736 Label all_true;
1737 __ bnz_b(i.InputSimd128Register(0), &all_true);
1738 __ li(dst, -1);
1739 __ li(dst, 0);
1740 __ bind(&all_true);
1741 break;
1742 }
1743 case kMipsMsaLd: {
1744 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1745 __ ld_b(i.OutputSimd128Register(), i.MemoryOperand());
1746 break;
1747 }
1748 case kMipsMsaSt: {
1749 CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
1750 __ st_b(i.InputSimd128Register(2), i.MemoryOperand());
1751 break;
1752 }
1677 } 1753 }
1678 return kSuccess; 1754 return kSuccess;
1679 } // NOLINT(readability/fn_size) 1755 } // NOLINT(readability/fn_size)
1680 1756
1681 1757
1682 #define UNSUPPORTED_COND(opcode, condition) \ 1758 #define UNSUPPORTED_COND(opcode, condition) \
1683 OFStream out(stdout); \ 1759 OFStream out(stdout); \
1684 out << "Unsupported " << #opcode << " condition: \"" << condition << "\""; \ 1760 out << "Unsupported " << #opcode << " condition: \"" << condition << "\""; \
1685 UNIMPLEMENTED(); 1761 UNIMPLEMENTED();
1686 1762
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2463 padding_size -= v8::internal::Assembler::kInstrSize; 2539 padding_size -= v8::internal::Assembler::kInstrSize;
2464 } 2540 }
2465 } 2541 }
2466 } 2542 }
2467 2543
2468 #undef __ 2544 #undef __
2469 2545
2470 } // namespace compiler 2546 } // namespace compiler
2471 } // namespace internal 2547 } // namespace internal
2472 } // namespace v8 2548 } // namespace v8
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