MIPS[64]: Support for some SIMD operations (8)

test/cctest/test-disasm-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1113 matching lines @@
   SET_UP();
   if (IsMipsArchVariant(kMips32r6) && CpuFeatures::IsSupported(MIPS_SIMD)) {
     CpuFeatureScope fscope(&assm, MIPS_SIMD);
 
     COMPARE_MSA_BRANCH(bnz_b(w0, 1), "47800001       bnz.b  w0, 1", 1);
     COMPARE_MSA_BRANCH(bnz_h(w1, -1), "47a1ffff       bnz.h  w1, -1", -1);
     COMPARE_MSA_BRANCH(bnz_w(w2, 32767), "47c27fff       bnz.w  w2, 32767",
                        32767);
     COMPARE_MSA_BRANCH(bnz_d(w3, -32768), "47e38000       bnz.d  w3, -32768",
                        -32768);
-    COMPARE_MSA_BRANCH(bnz_v(w0, 0), "45e00000       bnz.v  w0, 0", 0);
+    COMPARE_MSA_BRANCH(bnz_v(w0, (int16_t)0), "45e00000       bnz.v  w0, 0", 0);

[ivica.bogosavljevic, 2017/05/15 14:59:06]

use static_cast<int16_t> like the others

[dusan.simicic, 2017/05/19 08:55:01]

Done.

     COMPARE_MSA_BRANCH(bz_b(w0, 1), "47000001       bz.b  w0, 1", 1);
     COMPARE_MSA_BRANCH(bz_h(w1, -1), "4721ffff       bz.h  w1, -1", -1);
     COMPARE_MSA_BRANCH(bz_w(w2, 32767), "47427fff       bz.w  w2, 32767",
                        32767);
     COMPARE_MSA_BRANCH(bz_d(w3, -32768), "47638000       bz.d  w3, -32768",
                        -32768);
-    COMPARE_MSA_BRANCH(bz_v(w0, 0), "45600000       bz.v  w0, 0", 0);
+    COMPARE_MSA_BRANCH(bz_v(w0, (int16_t)0), "45600000       bz.v  w0, 0", 0);
   }
   VERIFY_RUN();
 }
 
 TEST(MSA_MI10) {
   SET_UP();
   if (IsMipsArchVariant(kMips32r6) && CpuFeatures::IsSupported(MIPS_SIMD)) {
     CpuFeatureScope fscope(&assm, MIPS_SIMD);
 
     COMPARE(ld_b(w0, MemOperand(at, -512)),
@@ skipping 640 matching lines @@
     COMPARE(srli_h(w31, w31, 2), "7962ffc9       srli.h  w31, w31, 2");
     COMPARE(srli_w(w5, w9, 4), "79444949       srli.w  w5, w9, 4");
     COMPARE(srli_d(w27, w26, 5), "7905d6c9       srli.d  w27, w26, 5");
     COMPARE(srlri_b(w18, w3, 0), "79f01c8a       srlri.b  w18, w3, 0");
     COMPARE(srlri_h(w1, w2, 3), "79e3104a       srlri.h  w1, w2, 3");
     COMPARE(srlri_w(w11, w22, 2), "79c2b2ca       srlri.w  w11, w22, 2");
     COMPARE(srlri_d(w24, w10, 6), "7986560a       srlri.d  w24, w10, 6");
   }
   VERIFY_RUN();
 }