[WASM SIMD] Implement packing and unpacking integer conversions.

[WASM SIMD] Implement packing and unpacking integer conversions.

- Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High,
  I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of
  an I16x8 register into a whole I32x4 register, with signed or unsigned
  extension. Having separate Low/High opcodes works around the difficulty
  of having multiple output registers, which would be necessary if we unpacked
  the entire I16x8 register.

- Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High,
  I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above.

- Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4,
  I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers
  into a single destination register with signed or unsigned saturation. These
  could have been separated into half operations, but this is simpler to
  implement with SSE, AVX, and is acceptable on ARM. It also avoids adding
  operations that only modify half of their destination register.

- Implements these opcodes for ARM.

LOG=N
BUG=v8:6020
Review-Url: https://codereview.chromium.org/2800523002
Cr-Commit-Position: refs/heads/master@{#44541}
Committed: https://chromium.googlesource.com/v8/v8/+/dbfc03005761b0f78ede078a00f0cc0a898fe8bd

[bbudge, 2017-04-04 23:59:02]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-04-04 23:59:13]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-05 00:04:32]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-04-05 00:04:32]

Dry run: Try jobs failed on following builders:
  v8_linux64_gyp_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_gyp_rel_ng/build...)

[bbudge, 2017-04-05 00:19:41]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-04-05 00:19:52]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[bbudge, 2017-04-05 00:32:18]

Description was changed from

==========
[WASM SIMD] Implement packing and unpacking integer conversions.

- Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High,
  I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of
  an I16x8 register into a whole I32x4 register, with signed or
  unsigned saturation. Having separate Low/High opcodes works around
  the difficulty of having multiple output registers, which would be
  necessary if we unpacked the entire I16x8 register.

- Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High,
  I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above.

- Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4,
  I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers
  into a single destination register. These could have been separated
  into half operations, but this is simpler to implement with SSE, AVX,
  and is acceptable on ARM. It also avoids adding operations that only
  modify half of their destination register.

- Implements these opcodes for ARM.

LOG=N
BUG=v8:6020
==========

to

==========
[WASM SIMD] Implement packing and unpacking integer conversions.

- Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High,
  I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of
  an I16x8 register into a whole I32x4 register, with signed or unsigned
  extension. Having separate Low/High opcodes works around the difficulty
  of having multiple output registers, which would be necessary if we unpacked
  the entire I16x8 register.

- Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High,
  I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above.

- Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4,
  I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers
  into a single destination register with signed or unsigned saturation. These
  could have been separated into half operations, but this is simpler to
  implement with SSE, AVX, and is acceptable on ARM. It also avoids adding
  operations that only modify half of their destination register.

- Implements these opcodes for ARM.

LOG=N
BUG=v8:6020
==========

[bbudge, 2017-04-05 00:34:54]

bbudge@chromium.org changed reviewers:
+ bmeurer@chromium.org, bradnelson@chromium.org, martyn.capewell@arm.com

[bbudge, 2017-04-05 00:34:54]

Martyn for src/compiler/arm
Benedikt for src/compiler and the rest if possible
Brad for src/wasm and the rest if possible

[commit-bot: I haz the power, 2017-04-05 00:43:46]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-04-05 00:43:46]

Dry run: This issue passed the CQ dry run.

[martyn.capewell, 2017-04-06 14:37:43]

https://codereview.chromium.org/2800523002/diff/20001/src/compiler/arm/code-g...
File src/compiler/arm/code-generator-arm.cc (right):

https://codereview.chromium.org/2800523002/diff/20001/src/compiler/arm/code-g...
src/compiler/arm/code-generator-arm.cc:1821: src1 = i.InputSimd128Register(0),
Name these src0 and src1 to match the input index.

https://codereview.chromium.org/2800523002/diff/20001/src/compiler/arm/code-g...
src/compiler/arm/code-generator-arm.cc:1824: if (dst.is(src1) || dst.is(src2)) {
By changing the operation order, I think you can avoid the scratch register and
extra move. Roughly, untested:

if (dst.is(src1) && dst.is(src2)) {
  vqmovn(dst.low(), src1);
  vmov(dst.high(), dst.low());
} else if (dst.is(src1)) {
  DCHECK(!dst.is(src2));
  vqmovn(dst.low(), src1);
  vqmovn(dst.high(), src2);
} else {
  DCHECK(!dst.is(src1));
  // dst may alias src2, so handle src2 first.
  vqmovn(dst.high(), src2);
  vqmovn(dst.low(), src1);
}

[bbudge, 2017-04-06 18:19:32]

https://codereview.chromium.org/2800523002/diff/20001/src/compiler/arm/code-g...
File src/compiler/arm/code-generator-arm.cc (right):

https://codereview.chromium.org/2800523002/diff/20001/src/compiler/arm/code-g...
src/compiler/arm/code-generator-arm.cc:1821: src1 = i.InputSimd128Register(0),
On 2017/04/06 14:37:43, martyn.capewell wrote:
> Name these src0 and src1 to match the input index.

Done.

https://codereview.chromium.org/2800523002/diff/20001/src/compiler/arm/code-g...
src/compiler/arm/code-generator-arm.cc:1824: if (dst.is(src1) || dst.is(src2)) {
On 2017/04/06 14:37:43, martyn.capewell wrote:
> By changing the operation order, I think you can avoid the scratch register
and
> extra move. Roughly, untested:
> 
> if (dst.is(src1) && dst.is(src2)) {
>   vqmovn(dst.low(), src1);
>   vmov(dst.high(), dst.low());
> } else if (dst.is(src1)) {
>   DCHECK(!dst.is(src2));
>   vqmovn(dst.low(), src1);
>   vqmovn(dst.high(), src2);
> } else {
>   DCHECK(!dst.is(src1));
>   // dst may alias src2, so handle src2 first.
>   vqmovn(dst.high(), src2);
>   vqmovn(dst.low(), src1);
> }

Nice. Done.

[bbudge, 2017-04-06 18:29:49]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-04-06 18:29:59]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-06 18:54:54]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-04-06 18:54:55]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-04-09 18:48:11]

PTAL

[Benedikt Meurer, 2017-04-10 04:10:15]

compiler LGTM

[martyn.capewell, 2017-04-10 10:13:39]

lgtm

[bbudge, 2017-04-10 19:07:02]

bbudge@chromium.org changed reviewers:
+ mtrofin@google.com
- bradnelson@chromium.org

[bbudge, 2017-04-10 19:07:02]

-Brad
+Mircea This adds some new SIMD ops to convert between the various sizes of
integer.

[Mircea Trofin, 2017-04-10 19:16:38]

mtrofin@chromium.org changed reviewers:
+ mtrofin@chromium.org

[Mircea Trofin, 2017-04-10 19:16:38]

lgtm for wasm

[bbudge, 2017-04-10 21:44:19]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-04-10 21:44:29]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-10 22:21:46]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-04-10 22:21:47]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-04-10 22:22:56]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-04-10 22:23:06]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-10 22:48:25]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-04-10 22:48:26]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-04-10 23:04:50]

The CQ bit was checked by bbudge@chromium.org

[bbudge, 2017-04-10 23:04:51]

The patchset sent to the CQ was uploaded after l-g-t-m from
bmeurer@chromium.org, martyn.capewell@arm.com, mtrofin@chromium.org
Link to the patchset: https://codereview.chromium.org/2800523002/#ps100001
(title: "Remove extraneous fn signature.")

[commit-bot: I haz the power, 2017-04-10 23:04:56]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-10 23:07:31]

CQ is committing da patch.

Bot data: {"patchset_id": 100001, "attempt_start_ts": 1491865490509010,
"parent_rev": "5f7e633113d4230613a893b482eae7707c543fa7", "commit_rev":
"dbfc03005761b0f78ede078a00f0cc0a898fe8bd"}

[commit-bot: I haz the power, 2017-04-10 23:07:38]

Description was changed from

==========
[WASM SIMD] Implement packing and unpacking integer conversions.

- Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High,
  I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of
  an I16x8 register into a whole I32x4 register, with signed or unsigned
  extension. Having separate Low/High opcodes works around the difficulty
  of having multiple output registers, which would be necessary if we unpacked
  the entire I16x8 register.

- Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High,
  I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above.

- Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4,
  I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers
  into a single destination register with signed or unsigned saturation. These
  could have been separated into half operations, but this is simpler to
  implement with SSE, AVX, and is acceptable on ARM. It also avoids adding
  operations that only modify half of their destination register.

- Implements these opcodes for ARM.

LOG=N
BUG=v8:6020
==========

to

==========
[WASM SIMD] Implement packing and unpacking integer conversions.

- Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High,
  I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of
  an I16x8 register into a whole I32x4 register, with signed or unsigned
  extension. Having separate Low/High opcodes works around the difficulty
  of having multiple output registers, which would be necessary if we unpacked
  the entire I16x8 register.

- Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High,
  I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above.

- Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4,
  I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers
  into a single destination register with signed or unsigned saturation. These
  could have been separated into half operations, but this is simpler to
  implement with SSE, AVX, and is acceptable on ARM. It also avoids adding
  operations that only modify half of their destination register.

- Implements these opcodes for ARM.

LOG=N
BUG=v8:6020

Review-Url: https://codereview.chromium.org/2800523002
Cr-Commit-Position: refs/heads/master@{#44541}
Committed:
https://chromium.googlesource.com/v8/v8/+/dbfc03005761b0f78ede078a00f0cc0a898...
==========

[commit-bot: I haz the power, 2017-04-10 23:07:39]

Committed patchset #6 (id:100001) as
https://chromium.googlesource.com/v8/v8/+/dbfc03005761b0f78ede078a00f0cc0a898...