MIPS[64]: Support for some SIMD operations (4)

MIPS[64]: Support for some SIMD operations (4)

Add support for F32x4Abs, F32x4Neg, F32x4RecipApprox,
F32x4RecipRefine, F32x4RecipSqrtApprox, F32x4RecipSqrtRefine,
F32x4Add, F32x4Sub, F32x4Mul, F32x4Max, F32x4Min,
F32x4Eq, F32x4Ne, F32x4Lt, F32x4Le, I32x4SConvertF32x4,
I32x4UConvertF32x4 operations for mips32 and mips64
architectures.

BUG=

Review-Url: https://codereview.chromium.org/2778203002
Cr-Commit-Position: refs/heads/master@{#44597}
Committed: https://chromium.googlesource.com/v8/v8/+/8d2db536c9025f9bf18cc2f5422d752bff764135

[dusan.simicic, 2017-03-28 12:36:28]

dusan.simicic@imgtec.com changed reviewers:
+ bbudge@chromium.org, ivica.bogosavljevic@imgtec.com, mtrofin@chromium.org,
titzer@chromium.org, v8-mips-ports@googlegroups.com

[dusan.simicic, 2017-03-28 12:36:29]

PTAL

[bbudge, 2017-03-28 17:21:40]

lgtm

https://codereview.chromium.org/2778203002/diff/1/src/compiler/mips/code-gene...
File src/compiler/mips/code-generator-mips.cc (right):

https://codereview.chromium.org/2778203002/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1627: __ fsub_w(dst,
kSimd128ScratchReg, dst);
I didn't realize until now that only ARM has refinement instructions, and they
have to be emulated on other platforms as you do here. That makes me think we
should remove these instructions, since these sequences are better left to the
programmer, who can schedule them to reduce stalling.

This is fine for now, just a heads up. What do you think about eliminating the
refine instructions?

https://codereview.chromium.org/2778203002/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1645: __ fmul_w(dst, dst,
kSimd128ScratchReg);
Same comment here, and for MIPS64.

[dusan.simicic, 2017-03-29 12:19:33]

https://codereview.chromium.org/2778203002/diff/1/src/compiler/mips/code-gene...
File src/compiler/mips/code-generator-mips.cc (right):

https://codereview.chromium.org/2778203002/diff/1/src/compiler/mips/code-gene...
src/compiler/mips/code-generator-mips.cc:1627: __ fsub_w(dst,
kSimd128ScratchReg, dst);

From MIPS perspective, it is better not to implement those refinement
operations, as we don't have corresponding MSA instructions. Also, I didn't find
anything about Float32x4RecipRefine and Float32x4RecipSqrtRefine requirements on
the following pages: 

https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Global_Obje...

tc39.github.io/ecmascript_simd/

https://github.com/stoklund/portable-simd/blob/master/webassembly-mapping.md

Are you familiar that refinement operations are mandatory by some other
document?
 
Maybe it's better to open an issue on WASM/design github page and involve other
people in discussion.

[dusan.simicic, 2017-04-03 13:06:15]

Description was changed from

==========
MIPS[64]: Support for some SIMD operations (4)

Add support for Float32x4Abs, Float32x4Neg, Float32x4RecipApprox,
Float32x4RecipRefine, Float32x4RecipSqrtApprox, Float32x4RecipSqrtRefine,
Float32x4Add, Float32x4Sub, Float32x4Mul, Float32x4Max, Float32x4Min,
Float32xEqual, Float32x4NotEqual, Float32xLessThan, Float32xLessThanOrEqual,
Int32x4FromFloat32x4, Uint32x4FromFloat32x4 operations for mips32 and mips64
architectures.

BUG=
==========

to

==========
MIPS[64]: Support for some SIMD operations (4)

Add support for F32x4Abs, F32x4Neg, F32x4RecipApprox,
F32x4RecipRefine, F32x4RecipSqrtApprox, F32x4RecipSqrtRefine,
F32x4Add, F32x4Sub, F32x4Mul, F32x4Max, F32x4Min,
F32x4Eq, F32x4Ne, F32x4Lt, F32x4Le, I32x4SConvertF32x4, I32x4UConvertF32x4
operations for mips32 and mips64
architectures.

BUG=
==========

[dusan.simicic, 2017-04-04 07:44:40]

Description was changed from

==========
MIPS[64]: Support for some SIMD operations (4)

Add support for F32x4Abs, F32x4Neg, F32x4RecipApprox,
F32x4RecipRefine, F32x4RecipSqrtApprox, F32x4RecipSqrtRefine,
F32x4Add, F32x4Sub, F32x4Mul, F32x4Max, F32x4Min,
F32x4Eq, F32x4Ne, F32x4Lt, F32x4Le, I32x4SConvertF32x4, I32x4UConvertF32x4
operations for mips32 and mips64
architectures.

BUG=
==========

to

==========
MIPS[64]: Support for some SIMD operations (4)

Add support for F32x4Abs, F32x4Neg, F32x4RecipApprox,
F32x4RecipRefine, F32x4RecipSqrtApprox, F32x4RecipSqrtRefine,
F32x4Add, F32x4Sub, F32x4Mul, F32x4Max, F32x4Min,
F32x4Eq, F32x4Ne, F32x4Lt, F32x4Le, I32x4SConvertF32x4,
I32x4UConvertF32x4 operations for mips32 and mips64
architectures.

BUG=
==========

[ivica.bogosavljevic, 2017-04-06 06:26:14]

MIPS part lgtm

https://codereview.chromium.org/2778203002/diff/20001/src/mips/assembler-mips.h
File src/mips/assembler-mips.h (right):

https://codereview.chromium.org/2778203002/diff/20001/src/mips/assembler-mips...
src/mips/assembler-mips.h:359: // MSA zero and scratch regs must have the same
numbers as FPU zero and scratch
why?

[dusan.simicic, 2017-04-06 11:20:17]

https://codereview.chromium.org/2778203002/diff/20001/src/mips/assembler-mips.h
File src/mips/assembler-mips.h (right):

https://codereview.chromium.org/2778203002/diff/20001/src/mips/assembler-mips...
src/mips/assembler-mips.h:359: // MSA zero and scratch regs must have the same
numbers as FPU zero and scratch
On 2017/04/06 06:26:14, ivica.bogosavljevic wrote:
> why?

We are using kSimpleFPAliasing register allocation scheme. SIMD, double and
float registers are overlapped in that scheme, so f28 (w28) and f30 (w30) are
reserved for zero and scratch.

[dusan.simicic, 2017-04-11 13:44:27]

dusan.simicic@imgtec.com changed reviewers:
+ tebbi@google.com

[dusan.simicic, 2017-04-11 13:44:27]

+ tebbi for instruction-selector.cc

[Tobias Tebbi, 2017-04-11 14:07:30]

On 2017/04/11 13:44:27, dusan.simicic wrote:
> + tebbi for instruction-selector.cc

instruction-selector.cc lgtm

[dusan.simicic, 2017-04-11 14:17:48]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2017-04-11 14:17:59]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-11 14:40:48]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-04-11 14:40:49]

Dry run: This issue passed the CQ dry run.

[dusan.simicic, 2017-04-12 07:29:55]

The CQ bit was checked by dusan.simicic@imgtec.com

[dusan.simicic, 2017-04-12 07:29:55]

The patchset sent to the CQ was uploaded after l-g-t-m from bbudge@chromium.org,
ivica.bogosavljevic@imgtec.com
Link to the patchset: https://codereview.chromium.org/2778203002/#ps40001
(title: "rebased")

[commit-bot: I haz the power, 2017-04-12 07:30:00]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-12 07:32:01]

CQ is committing da patch.

Bot data: {"patchset_id": 40001, "attempt_start_ts": 1491982195238140,
"parent_rev": "a615efaa50ae5870e7f52e098e96570093b9fce5", "commit_rev":
"8d2db536c9025f9bf18cc2f5422d752bff764135"}

[commit-bot: I haz the power, 2017-04-12 07:32:07]

Description was changed from

==========
MIPS[64]: Support for some SIMD operations (4)

Add support for F32x4Abs, F32x4Neg, F32x4RecipApprox,
F32x4RecipRefine, F32x4RecipSqrtApprox, F32x4RecipSqrtRefine,
F32x4Add, F32x4Sub, F32x4Mul, F32x4Max, F32x4Min,
F32x4Eq, F32x4Ne, F32x4Lt, F32x4Le, I32x4SConvertF32x4,
I32x4UConvertF32x4 operations for mips32 and mips64
architectures.

BUG=
==========

to

==========
MIPS[64]: Support for some SIMD operations (4)

Add support for F32x4Abs, F32x4Neg, F32x4RecipApprox,
F32x4RecipRefine, F32x4RecipSqrtApprox, F32x4RecipSqrtRefine,
F32x4Add, F32x4Sub, F32x4Mul, F32x4Max, F32x4Min,
F32x4Eq, F32x4Ne, F32x4Lt, F32x4Le, I32x4SConvertF32x4,
I32x4UConvertF32x4 operations for mips32 and mips64
architectures.

BUG=

Review-Url: https://codereview.chromium.org/2778203002
Cr-Commit-Position: refs/heads/master@{#44597}
Committed:
https://chromium.googlesource.com/v8/v8/+/8d2db536c9025f9bf18cc2f5422d752bff7...
==========

[commit-bot: I haz the power, 2017-04-12 07:32:08]

Committed patchset #3 (id:40001) as
https://chromium.googlesource.com/v8/v8/+/8d2db536c9025f9bf18cc2f5422d752bff7...