MIPS[64]: Support for some SIMD operations (4)

src/mips/assembler-mips.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 338 matching lines @@
 // Register aliases.
 // cp is assumed to be a callee saved register.
 constexpr Register kRootRegister = s6;
 constexpr Register cp = s7;
 constexpr Register kLithiumScratchReg = s3;
 constexpr Register kLithiumScratchReg2 = s4;
 constexpr DoubleRegister kLithiumScratchDouble = f30;
 constexpr DoubleRegister kDoubleRegZero = f28;
 // Used on mips32r6 for compare operations.
 constexpr DoubleRegister kDoubleCompareReg = f26;
+// MSA zero and scratch regs must have the same numbers as FPU zero and scratch

[ivica.bogosavljevic, 2017/04/06 06:26:14]

why?

[dusan.simicic, 2017/04/06 11:20:17]

We are using kSimpleFPAliasing register allocation scheme. SIMD, double and
float registers are overlapped in that scheme, so f28 (w28) and f30 (w30) are
reserved for zero and scratch.    

+constexpr Simd128Register kSimd128RegZero = w28;
+constexpr Simd128Register kSimd128ScratchReg = w30;
 
 // FPU (coprocessor 1) control registers.
 // Currently only FCSR (#31) is implemented.
 struct FPUControlRegister {
   bool is_valid() const { return reg_code == kFCSRRegister; }
   bool is(FPUControlRegister creg) const { return reg_code == creg.reg_code; }
   int code() const {
     DCHECK(is_valid());
     return reg_code;
   }
@@ skipping 1830 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_ASSEMBLER_MIPS_H_