src/mips64/assembler-mips64.h - Issue 2778203002: MIPS[64]: Support for some SIMD operations (4)

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Unified Diff: src/mips64/assembler-mips64.h

Issue 2778203002: MIPS[64]: Support for some SIMD operations (4) (Closed)

Patch Set: rebased Created 3 years, 8 months ago

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Index: src/mips64/assembler-mips64.h

diff --git a/src/mips64/assembler-mips64.h b/src/mips64/assembler-mips64.h

index a57a566b21c5f95e97ef6388b74b65d28aaf78ae..931ae4c7871af3be97a9e7fa3c8bf76a927468d6 100644

--- a/src/mips64/assembler-mips64.h

+++ b/src/mips64/assembler-mips64.h

@@ -361,6 +361,9 @@ constexpr DoubleRegister kDoubleRegZero = f28;

// Used on mips64r6 for compare operations.

// We use the last non-callee saved odd register for N64 ABI

constexpr DoubleRegister kDoubleCompareReg = f23;

+// MSA zero and scratch regs must have the same numbers as FPU zero and scratch

+constexpr Simd128Register kSimd128RegZero = w28;

+constexpr Simd128Register kSimd128ScratchReg = w30;

// FPU (coprocessor 1) control registers.

// Currently only FCSR (#31) is implemented.

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