[ARM] Implement more NEON permutation instructions.

[ARM] Implement more NEON permutation instructions.
- Implements vuzp, vtrn instructions for q-registers.
- Refactors vmvn, vswp to use common unary op helper fn.

LOG=N
BUG=v8:6020
Review-Url: https://codereview.chromium.org/2739033002
Cr-Commit-Position: refs/heads/master@{#43795}
Committed: https://chromium.googlesource.com/v8/v8/+/a75f7cd344ea14ec65d80a3138823e0b12170991

[bbudge, 2017-03-09 00:47:10]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-03-09 00:47:13]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[bbudge, 2017-03-09 00:50:05]

bbudge@chromium.org changed reviewers:
+ martyn.capewell@arm.com

[commit-bot: I haz the power, 2017-03-09 01:11:53]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-03-09 01:11:54]

Dry run: This issue passed the CQ dry run.

[martyn.capewell, 2017-03-09 14:03:36]

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc
File src/arm/assembler-arm.cc (right):

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc#ne...
src/arm/assembler-arm.cc:4122: int vd = dst_code & 0x0F;
Perhaps there should be some static methods to split register codes based on
whether the value represents a S, D or Q register, then use them here, below,
and also refactor QwNeonRegister::split_code() etc to use them.

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc#ne...
src/arm/assembler-arm.cc:4716: op_encoding = 0x2 * B16 | B8 | B7;
Some of these seem inconsistently expressed. For example B8 | B7 == 0x3 * B7 and
B8 == 0x2 * B7.

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.h
File src/arm/assembler-arm.h (right):

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.h#new...
src/arm/assembler-arm.h:1319: // Only unconditional vdup is currently supported.
The conditional form of this vdup is deprecated, so you can either update or
remove this comment - see ARM ARM (DDI0406C) page A8-288.

[bbudge, 2017-03-09 20:48:08]

The CQ bit was checked by bbudge@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-03-09 20:48:15]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[bbudge, 2017-03-09 20:51:05]

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc
File src/arm/assembler-arm.cc (right):

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc#ne...
src/arm/assembler-arm.cc:4122: int vd = dst_code & 0x0F;
On 2017/03/09 14:03:36, martyn.capewell wrote:
> Perhaps there should be some static methods to split register codes based on
> whether the value represents a S, D or Q register, then use them here, below,
> and also refactor QwNeonRegister::split_code() etc to use them.

Good idea. Done.

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc#ne...
src/arm/assembler-arm.cc:4716: op_encoding = 0x2 * B16 | B8 | B7;
On 2017/03/09 14:03:36, martyn.capewell wrote:
> Some of these seem inconsistently expressed. For example B8 | B7 == 0x3 * B7
and
> B8 == 0x2 * B7.

Done.

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.h
File src/arm/assembler-arm.h (right):

https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.h#new...
src/arm/assembler-arm.h:1319: // Only unconditional vdup is currently supported.
On 2017/03/09 14:03:36, martyn.capewell wrote:
> The conditional form of this vdup is deprecated, so you can either update or
> remove this comment - see ARM ARM (DDI0406C) page A8-288.

Done.

[commit-bot: I haz the power, 2017-03-09 21:15:08]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-03-09 21:15:09]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-03-13 17:23:51]

On 2017/03/09 20:51:05, bbudge wrote:
> https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc
> File src/arm/assembler-arm.cc (right):
> 
>
https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc#ne...
> src/arm/assembler-arm.cc:4122: int vd = dst_code & 0x0F;
> On 2017/03/09 14:03:36, martyn.capewell wrote:
> > Perhaps there should be some static methods to split register codes based on
> > whether the value represents a S, D or Q register, then use them here,
below,
> > and also refactor QwNeonRegister::split_code() etc to use them.
> 
> Good idea. Done.
> 
>
https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.cc#ne...
> src/arm/assembler-arm.cc:4716: op_encoding = 0x2 * B16 | B8 | B7;
> On 2017/03/09 14:03:36, martyn.capewell wrote:
> > Some of these seem inconsistently expressed. For example B8 | B7 == 0x3 * B7
> and
> > B8 == 0x2 * B7.
> 
> Done.
> 
> https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.h
> File src/arm/assembler-arm.h (right):
> 
>
https://codereview.chromium.org/2739033002/diff/1/src/arm/assembler-arm.h#new...
> src/arm/assembler-arm.h:1319: // Only unconditional vdup is currently
supported.
> On 2017/03/09 14:03:36, martyn.capewell wrote:
> > The conditional form of this vdup is deprecated, so you can either update or
> > remove this comment - see ARM ARM (DDI0406C) page A8-288.
> 
> Done.

ping

[martyn.capewell, 2017-03-13 17:25:31]

lgtm

[bbudge, 2017-03-14 16:07:24]

The CQ bit was checked by bbudge@chromium.org

[commit-bot: I haz the power, 2017-03-14 16:07:30]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-03-14 16:28:46]

CQ is committing da patch.

Bot data: {"patchset_id": 20001, "attempt_start_ts": 1489507644294980,
"parent_rev": "af63679d0531992f70ed96db58b72b1b3449aa48", "commit_rev":
"a75f7cd344ea14ec65d80a3138823e0b12170991"}

[commit-bot: I haz the power, 2017-03-14 16:28:51]

Description was changed from

==========
[ARM] Implement more NEON permutation instructions.
- Implements vuzp, vtrn instructions for q-registers.
- Refactors vmvn, vswp to use common unary op helper fn.

LOG=N
BUG=v8:6020
==========

to

==========
[ARM] Implement more NEON permutation instructions.
- Implements vuzp, vtrn instructions for q-registers.
- Refactors vmvn, vswp to use common unary op helper fn.

LOG=N
BUG=v8:6020

Review-Url: https://codereview.chromium.org/2739033002
Cr-Commit-Position: refs/heads/master@{#43795}
Committed:
https://chromium.googlesource.com/v8/v8/+/a75f7cd344ea14ec65d80a3138823e0b121...
==========

[commit-bot: I haz the power, 2017-03-14 16:28:52]

Committed patchset #2 (id:20001) as
https://chromium.googlesource.com/v8/v8/+/a75f7cd344ea14ec65d80a3138823e0b121...