[ARM] Implement more NEON permutation instructions.

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 2213 matching lines @@
           int Vn = instr->VFPNRegValue(kDoublePrecision);
           int Vm = instr->VFPMRegValue(kDoublePrecision);
           int len = instr->Bits(9, 8);
           NeonListOperand list(DwVfpRegister::from_code(Vn), len + 1);
           out_buffer_pos_ +=
               SNPrintF(out_buffer_ + out_buffer_pos_, "%s d%d, ",
                        instr->Bit(6) == 0 ? "vtbl.8" : "vtbx.8", Vd);
           FormatNeonList(Vn, list.type());
           Print(", ");
           PrintDRegister(Vm);
-        } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 6) == 0x7) {
+        } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 8) == 0x1 &&
+                   instr->Bit(6) == 1) {
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           int size = kBitsPerByte * (1 << instr->Bits(19, 18));
-          // vzip.<size> Qd, Qm.
+          const char* op = instr->Bit(7) != 0 ? "vzip" : "vuzp";
+          // vzip/vuzp.<size> Qd, Qm.
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                      "vzip.%d q%d, q%d", size, Vd, Vm);
-        } else if (instr->Bits(17, 16) == 0 && instr->Bits(11, 9) == 0) {
+                                      "%s.%d q%d, q%d", op, size, Vd, Vm);
+        } else if (instr->Bits(17, 16) == 0 && instr->Bits(11, 9) == 0 &&
+                   instr->Bit(6) == 1) {
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           int size = kBitsPerByte * (1 << instr->Bits(19, 18));
           int op = kBitsPerByte
                    << (static_cast<int>(Neon64) - instr->Bits(8, 7));
           // vrev<op>.<size> Qd, Qm.
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                       "vrev%d.%d q%d, q%d", op, size, Vd, Vm);
-        } else if (instr->Bits(17, 16) == 0x1 && instr->Bit(11) == 0) {
+        } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 6) == 0x3) {
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           int size = kBitsPerByte * (1 << instr->Bits(19, 18));
+          // vtrn.<size> Qd, Qm.
+          out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "vtrn.%d q%d, q%d", size, Vd, Vm);
+        } else if (instr->Bits(17, 16) == 0x1 && instr->Bit(11) == 0 &&
+                   instr->Bit(6) == 1) {
+          int Vd = instr->VFPDRegValue(kSimd128Precision);
+          int Vm = instr->VFPMRegValue(kSimd128Precision);
+          int size = kBitsPerByte * (1 << instr->Bits(19, 18));
           const char* type = instr->Bit(10) != 0 ? "f" : "s";
           if (instr->Bits(9, 6) == 0xd) {
             // vabs<type>.<size> Qd, Qm.
             out_buffer_pos_ +=
                 SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%s%d q%d, q%d",
                          type, size, Vd, Vm);
           } else if (instr->Bits(9, 6) == 0xf) {
             // vneg<type>.<size> Qd, Qm.
             out_buffer_pos_ +=
                 SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%s%d q%d, q%d",
                          type, size, Vd, Vm);
           } else {
             Unknown(instr);
           }
-        } else if (instr->Bits(19, 18) == 0x2 && instr->Bits(11, 8) == 0x5) {
+        } else if (instr->Bits(19, 18) == 0x2 && instr->Bits(11, 8) == 0x5 &&
+                   instr->Bit(6) == 1) {
           // vrecpe/vrsqrte.f32 Qd, Qm.
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           const char* op = instr->Bit(7) == 0 ? "vrecpe" : "vrsqrte";
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                       "%s.f32 q%d, q%d", op, Vd, Vm);
         } else {
           Unknown(instr);
         }
-      } else if (instr->Bits(11, 7) == 0 && instr->Bit(4) == 1) {
+      } else if (instr->Bits(11, 7) == 0 && instr->Bit(4) == 1 &&
+                 instr->Bit(6) == 1) {
         // vshr.u<size> Qd, Qm, shift
         int size = base::bits::RoundDownToPowerOfTwo32(instr->Bits(21, 16));
         int shift = 2 * size - instr->Bits(21, 16);
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         out_buffer_pos_ +=
             SNPrintF(out_buffer_ + out_buffer_pos_, "vshr.u%d q%d, q%d, #%d",
                      size, Vd, Vm, shift);
       } else {
         Unknown(instr);
@@ skipping 333 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM