MIPS: Fix improper use of odd FP reg on mips32r6

MIPS: Fix improper use of odd FP reg on mips32r6

Odd numbered floating-point register shouldn't be used as compare register
on mips32r6 architecture. In case cpu switches to FRE mode, writes to odd
numbered single-precision fp register will update upper part of even
double-precision register, which will corrupt the even register.

BUG=

Review-Url: https://codereview.chromium.org/2591063003
Cr-Commit-Position: refs/heads/master@{#41916}
Committed: https://chromium.googlesource.com/v8/v8/+/cc77bd8234a8aa2293c7a028571ae5e8d4d13134

[dusan.simicic, 2016-12-21 12:54:12]

dusan.simicic@imgtec.com changed reviewers:
+ ivica.bogosavljevic@imgtec.com, miran.karic@imgtec.com,
v8-mips-ports@googlegroups.com

[dusan.simicic, 2016-12-21 12:54:13]

PTAL

[ivica.bogosavljevic, 2016-12-21 13:52:39]

lgtm

[dusan.simicic, 2016-12-21 15:36:21]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2016-12-21 15:36:26]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-12-21 16:02:33]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2016-12-21 16:02:34]

Dry run: This issue passed the CQ dry run.

[dusan.simicic, 2016-12-22 10:04:33]

The CQ bit was unchecked by dusan.simicic@imgtec.com

[dusan.simicic, 2016-12-22 10:04:34]

The CQ bit was checked by dusan.simicic@imgtec.com

[commit-bot: I haz the power, 2016-12-22 10:04:42]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-12-22 10:06:19]

CQ is committing da patch.

Bot data: {"patchset_id": 1, "attempt_start_ts": 1482401074906240, "parent_rev":
"1e994192d6e5e441f6dc14596f25c7273651fba8", "commit_rev":
"cc77bd8234a8aa2293c7a028571ae5e8d4d13134"}

[commit-bot: I haz the power, 2016-12-22 10:06:23]

Description was changed from

==========
MIPS: Fix improper use of odd FP reg on mips32r6

Odd numbered floating-point register shouldn't be used as compare register
on mips32r6 architecture. In case cpu switches to FRE mode, writes to odd
numbered single-precision fp register will update upper part of even
double-precision register, which will corrupt the even register.

BUG=
==========

to

==========
MIPS: Fix improper use of odd FP reg on mips32r6

Odd numbered floating-point register shouldn't be used as compare register
on mips32r6 architecture. In case cpu switches to FRE mode, writes to odd
numbered single-precision fp register will update upper part of even
double-precision register, which will corrupt the even register.

BUG=

Review-Url: https://codereview.chromium.org/2591063003
Cr-Commit-Position: refs/heads/master@{#41916}
Committed:
https://chromium.googlesource.com/v8/v8/+/cc77bd8234a8aa2293c7a028571ae5e8d4d...
==========

[commit-bot: I haz the power, 2016-12-22 10:06:25]

Committed patchset #1 (id:1) as
https://chromium.googlesource.com/v8/v8/+/cc77bd8234a8aa2293c7a028571ae5e8d4d...