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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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61 V(f0) V(f1) V(f2) V(f3) V(f4) V(f5) V(f6) V(f7) \ | 61 V(f0) V(f1) V(f2) V(f3) V(f4) V(f5) V(f6) V(f7) \ |
62 V(f8) V(f9) V(f10) V(f11) V(f12) V(f13) V(f14) V(f15) \ | 62 V(f8) V(f9) V(f10) V(f11) V(f12) V(f13) V(f14) V(f15) \ |
63 V(f16) V(f17) V(f18) V(f19) V(f20) V(f21) V(f22) V(f23) \ | 63 V(f16) V(f17) V(f18) V(f19) V(f20) V(f21) V(f22) V(f23) \ |
64 V(f24) V(f25) V(f26) V(f27) V(f28) V(f29) V(f30) V(f31) | 64 V(f24) V(f25) V(f26) V(f27) V(f28) V(f29) V(f30) V(f31) |
65 | 65 |
66 #define FLOAT_REGISTERS DOUBLE_REGISTERS | 66 #define FLOAT_REGISTERS DOUBLE_REGISTERS |
67 #define SIMD128_REGISTERS DOUBLE_REGISTERS | 67 #define SIMD128_REGISTERS DOUBLE_REGISTERS |
68 | 68 |
69 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ | 69 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ |
70 V(f0) V(f2) V(f4) V(f6) V(f8) V(f10) V(f12) V(f14) \ | 70 V(f0) V(f2) V(f4) V(f6) V(f8) V(f10) V(f12) V(f14) \ |
71 V(f16) V(f18) V(f20) V(f22) V(f24) V(f26) | 71 V(f16) V(f18) V(f20) V(f22) V(f24) |
72 // clang-format on | 72 // clang-format on |
73 | 73 |
74 // CPU Registers. | 74 // CPU Registers. |
75 // | 75 // |
76 // 1) We would prefer to use an enum, but enum values are assignment- | 76 // 1) We would prefer to use an enum, but enum values are assignment- |
77 // compatible with int, which has caused code-generation bugs. | 77 // compatible with int, which has caused code-generation bugs. |
78 // | 78 // |
79 // 2) We would prefer to use a class instead of a struct but we don't like | 79 // 2) We would prefer to use a class instead of a struct but we don't like |
80 // the register initialization to depend on the particular initialization | 80 // the register initialization to depend on the particular initialization |
81 // order (which appears to be different on OS X, Linux, and Windows for the | 81 // order (which appears to be different on OS X, Linux, and Windows for the |
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275 // Defined using #define instead of "static const Register&" because Clang | 275 // Defined using #define instead of "static const Register&" because Clang |
276 // complains otherwise when a compilation unit that includes this header | 276 // complains otherwise when a compilation unit that includes this header |
277 // doesn't use the variables. | 277 // doesn't use the variables. |
278 #define kRootRegister s6 | 278 #define kRootRegister s6 |
279 #define cp s7 | 279 #define cp s7 |
280 #define kLithiumScratchReg s3 | 280 #define kLithiumScratchReg s3 |
281 #define kLithiumScratchReg2 s4 | 281 #define kLithiumScratchReg2 s4 |
282 #define kLithiumScratchDouble f30 | 282 #define kLithiumScratchDouble f30 |
283 #define kDoubleRegZero f28 | 283 #define kDoubleRegZero f28 |
284 // Used on mips32r6 for compare operations. | 284 // Used on mips32r6 for compare operations. |
285 // We use the last non-callee saved odd register for O32 ABI | 285 #define kDoubleCompareReg f26 |
286 #define kDoubleCompareReg f19 | |
287 | 286 |
288 // FPU (coprocessor 1) control registers. | 287 // FPU (coprocessor 1) control registers. |
289 // Currently only FCSR (#31) is implemented. | 288 // Currently only FCSR (#31) is implemented. |
290 struct FPUControlRegister { | 289 struct FPUControlRegister { |
291 bool is_valid() const { return reg_code == kFCSRRegister; } | 290 bool is_valid() const { return reg_code == kFCSRRegister; } |
292 bool is(FPUControlRegister creg) const { return reg_code == creg.reg_code; } | 291 bool is(FPUControlRegister creg) const { return reg_code == creg.reg_code; } |
293 int code() const { | 292 int code() const { |
294 DCHECK(is_valid()); | 293 DCHECK(is_valid()); |
295 return reg_code; | 294 return reg_code; |
296 } | 295 } |
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1476 public: | 1475 public: |
1477 explicit EnsureSpace(Assembler* assembler) { | 1476 explicit EnsureSpace(Assembler* assembler) { |
1478 assembler->CheckBuffer(); | 1477 assembler->CheckBuffer(); |
1479 } | 1478 } |
1480 }; | 1479 }; |
1481 | 1480 |
1482 } // namespace internal | 1481 } // namespace internal |
1483 } // namespace v8 | 1482 } // namespace v8 |
1484 | 1483 |
1485 #endif // V8_ARM_ASSEMBLER_MIPS_H_ | 1484 #endif // V8_ARM_ASSEMBLER_MIPS_H_ |
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