[Turbofan] Add ARM support for simd128 moves and swaps.

src/arm/constants-arm.h

Index: src/arm/constants-arm.h
diff --git a/src/arm/constants-arm.h b/src/arm/constants-arm.h
index 2bade20fedf5979475bc7d36ea1ba8f7a10c8095..9306194ac6b71971b384df78545f591aa1e2a5e5 100644
--- a/src/arm/constants-arm.h
+++ b/src/arm/constants-arm.h
@@ -374,10 +374,10 @@ const int32_t  kDefaultStopCode = -1;
 // Type of VFP register. Determines register encoding.
 enum VFPRegPrecision {
   kSinglePrecision = 0,
-  kDoublePrecision = 1
+  kDoublePrecision = 1,
+  kSimd128Precision = 2
 };
 
-
 // VFP FPSCR constants.
 enum VFPConversionMode {
   kFPSCRRounding = 0,
@@ -672,10 +672,13 @@ class Instruction {
   // bit specifier. one_bit is the position of the additional single bit
   // specifier.
   inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) {
-    if (pre == kSinglePrecision) {
+    if (pre == kDoublePrecision) {

[martyn.capewell, 2016/11/23 20:08:46]

As Q is encoded in the same way as D, but as Q*2, how about something like:
if (pre == kSinglePrecision) {
  return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
} else {
  int reg_num = (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
  if (pre == kDoublePrecision) {
    return reg_num;
  }
  DCHECK_EQ(kSimd128Precision, pre);
  DCHECK_EQ(reg_num & 1, 0);
  return reg_num / 2;
}

[bbudge, 2016/11/24 02:22:53]

Done.

+      return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
+    } else if (pre == kSinglePrecision) {
       return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
     }
-    return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
+    DCHECK_EQ(kSimd128Precision, pre);
+    return (Bit(one_bit) << 3) | Bits(four_bit + 3, four_bit) >> 1;
   }
 
   // We need to prevent the creation of instances of class Instruction.