| Index: runtime/vm/flow_graph_compiler_mips.cc
|
| ===================================================================
|
| --- runtime/vm/flow_graph_compiler_mips.cc (revision 25072)
|
| +++ runtime/vm/flow_graph_compiler_mips.cc (working copy)
|
| @@ -780,7 +780,7 @@
|
| __ sw(loc.reg(), dest);
|
| }
|
| } else {
|
| - Address src = loc.ToStackSlotAddress();
|
| + const Address& src = Address::StackSlotAddress(loc);
|
| if (!src.Equals(dest)) {
|
| if (!*push_emitted) {
|
| __ Push(T0);
|
| @@ -1817,22 +1817,22 @@
|
| __ mov(destination.reg(), source.reg());
|
| } else {
|
| ASSERT(destination.IsStackSlot());
|
| - __ sw(source.reg(), destination.ToStackSlotAddress());
|
| + __ sw(source.reg(), Address::StackSlotAddress(destination));
|
| }
|
| } else if (source.IsStackSlot()) {
|
| if (destination.IsRegister()) {
|
| - __ lw(destination.reg(), source.ToStackSlotAddress());
|
| + __ lw(destination.reg(), Address::StackSlotAddress(source));
|
| } else {
|
| ASSERT(destination.IsStackSlot());
|
| - MoveMemoryToMemory(destination.ToStackSlotAddress(),
|
| - source.ToStackSlotAddress());
|
| + MoveMemoryToMemory(Address::StackSlotAddress(destination),
|
| + Address::StackSlotAddress(source));
|
| }
|
| } else if (source.IsFpuRegister()) {
|
| if (destination.IsFpuRegister()) {
|
| __ movd(destination.fpu_reg(), source.fpu_reg());
|
| } else {
|
| if (destination.IsDoubleStackSlot()) {
|
| - const Address& addr = destination.ToStackSlotAddress();
|
| + const Address& addr = Address::StackSlotAddress(destination);
|
| int32_t offset = addr.offset();
|
| __ StoreDToOffset(source.fpu_reg(), FP, offset);
|
| } else {
|
| @@ -1842,14 +1842,14 @@
|
| }
|
| } else if (source.IsDoubleStackSlot()) {
|
| if (destination.IsFpuRegister()) {
|
| - const Address &addr = source.ToStackSlotAddress();
|
| + const Address &addr = Address::StackSlotAddress(source);
|
| const Register base = addr.base();
|
| const int32_t offset = addr.offset();
|
| __ LoadDFromOffset(destination.fpu_reg(), base, offset);
|
| } else {
|
| ASSERT(destination.IsDoubleStackSlot());
|
| - const Address& saddr = source.ToStackSlotAddress();
|
| - const Address& daddr = destination.ToStackSlotAddress();
|
| + const Address& saddr = Address::StackSlotAddress(source);
|
| + const Address& daddr = Address::StackSlotAddress(destination);
|
| int32_t soffset = saddr.offset();
|
| int32_t doffset = daddr.offset();
|
| __ LoadDFromOffset(FpuTMP, FP, soffset);
|
| @@ -1864,7 +1864,7 @@
|
| __ LoadObject(destination.reg(), constant);
|
| } else {
|
| ASSERT(destination.IsStackSlot());
|
| - StoreObject(destination.ToStackSlotAddress(), source.constant());
|
| + StoreObject(Address::StackSlotAddress(destination), source.constant());
|
| }
|
| }
|
|
|
| @@ -1885,11 +1885,12 @@
|
| __ mov(source.reg(), destination.reg());
|
| __ mov(destination.reg(), TMP1);
|
| } else if (source.IsRegister() && destination.IsStackSlot()) {
|
| - Exchange(source.reg(), destination.ToStackSlotAddress());
|
| + Exchange(source.reg(), Address::StackSlotAddress(destination));
|
| } else if (source.IsStackSlot() && destination.IsRegister()) {
|
| - Exchange(destination.reg(), source.ToStackSlotAddress());
|
| + Exchange(destination.reg(), Address::StackSlotAddress(source));
|
| } else if (source.IsStackSlot() && destination.IsStackSlot()) {
|
| - Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress());
|
| + Exchange(Address::StackSlotAddress(destination),
|
| + Address::StackSlotAddress(source));
|
| } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
|
| __ movd(FpuTMP, source.fpu_reg());
|
| __ movd(source.fpu_reg(), destination.fpu_reg());
|
| @@ -1904,8 +1905,8 @@
|
| DRegister reg = source.IsFpuRegister() ? source.fpu_reg()
|
| : destination.fpu_reg();
|
| const Address& slot_address = source.IsFpuRegister()
|
| - ? destination.ToStackSlotAddress()
|
| - : source.ToStackSlotAddress();
|
| + ? Address::StackSlotAddress(destination)
|
| + : Address::StackSlotAddress(source);
|
|
|
| if (double_width) {
|
| const Register base = slot_address.base();
|
| @@ -1917,8 +1918,9 @@
|
| UNIMPLEMENTED();
|
| }
|
| } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
|
| - const Address& source_slot_address = source.ToStackSlotAddress();
|
| - const Address& destination_slot_address = destination.ToStackSlotAddress();
|
| + const Address& source_slot_address = Address::StackSlotAddress(source);
|
| + const Address& destination_slot_address =
|
| + Address::StackSlotAddress(destination);
|
| const Register sbase = source_slot_address.base();
|
| const int32_t soffset = source_slot_address.offset();
|
| const Register dbase = destination_slot_address.base();
|
|
|