| Index: runtime/vm/flow_graph_compiler_x64.cc
|
| ===================================================================
|
| --- runtime/vm/flow_graph_compiler_x64.cc (revision 25072)
|
| +++ runtime/vm/flow_graph_compiler_x64.cc (working copy)
|
| @@ -767,7 +767,7 @@
|
| __ movq(dest, loc.reg());
|
| }
|
| } else {
|
| - Address src = loc.ToStackSlotAddress();
|
| + const Address& src = Address::StackSlotAddress(loc);
|
| if (!src.Equals(dest)) {
|
| if (!*push_emitted) {
|
| __ pushq(RAX);
|
| @@ -1723,15 +1723,15 @@
|
| __ movq(destination.reg(), source.reg());
|
| } else {
|
| ASSERT(destination.IsStackSlot());
|
| - __ movq(destination.ToStackSlotAddress(), source.reg());
|
| + __ movq(Address::StackSlotAddress(destination), source.reg());
|
| }
|
| } else if (source.IsStackSlot()) {
|
| if (destination.IsRegister()) {
|
| - __ movq(destination.reg(), source.ToStackSlotAddress());
|
| + __ movq(destination.reg(), Address::StackSlotAddress(source));
|
| } else {
|
| ASSERT(destination.IsStackSlot());
|
| - MoveMemoryToMemory(destination.ToStackSlotAddress(),
|
| - source.ToStackSlotAddress());
|
| + MoveMemoryToMemory(Address::StackSlotAddress(destination),
|
| + Address::StackSlotAddress(source));
|
| }
|
| } else if (source.IsFpuRegister()) {
|
| if (destination.IsFpuRegister()) {
|
| @@ -1740,27 +1740,27 @@
|
| __ movaps(destination.fpu_reg(), source.fpu_reg());
|
| } else {
|
| if (destination.IsDoubleStackSlot()) {
|
| - __ movsd(destination.ToStackSlotAddress(), source.fpu_reg());
|
| + __ movsd(Address::StackSlotAddress(destination), source.fpu_reg());
|
| } else {
|
| ASSERT(destination.IsQuadStackSlot());
|
| - __ movups(destination.ToStackSlotAddress(), source.fpu_reg());
|
| + __ movups(Address::StackSlotAddress(destination), source.fpu_reg());
|
| }
|
| }
|
| } else if (source.IsDoubleStackSlot()) {
|
| if (destination.IsFpuRegister()) {
|
| - __ movsd(destination.fpu_reg(), source.ToStackSlotAddress());
|
| + __ movsd(destination.fpu_reg(), Address::StackSlotAddress(source));
|
| } else {
|
| ASSERT(destination.IsDoubleStackSlot());
|
| - __ movsd(XMM0, source.ToStackSlotAddress());
|
| - __ movsd(destination.ToStackSlotAddress(), XMM0);
|
| + __ movsd(XMM0, Address::StackSlotAddress(source));
|
| + __ movsd(Address::StackSlotAddress(destination), XMM0);
|
| }
|
| } else if (source.IsQuadStackSlot()) {
|
| if (destination.IsFpuRegister()) {
|
| - __ movups(destination.fpu_reg(), source.ToStackSlotAddress());
|
| + __ movups(destination.fpu_reg(), Address::StackSlotAddress(source));
|
| } else {
|
| ASSERT(destination.IsQuadStackSlot());
|
| - __ movups(XMM0, source.ToStackSlotAddress());
|
| - __ movups(destination.ToStackSlotAddress(), XMM0);
|
| + __ movups(XMM0, Address::StackSlotAddress(source));
|
| + __ movups(Address::StackSlotAddress(destination), XMM0);
|
| }
|
| } else {
|
| ASSERT(source.IsConstant());
|
| @@ -1773,7 +1773,7 @@
|
| }
|
| } else {
|
| ASSERT(destination.IsStackSlot());
|
| - StoreObject(destination.ToStackSlotAddress(), source.constant());
|
| + StoreObject(Address::StackSlotAddress(destination), source.constant());
|
| }
|
| }
|
|
|
| @@ -1789,11 +1789,12 @@
|
| if (source.IsRegister() && destination.IsRegister()) {
|
| __ xchgq(destination.reg(), source.reg());
|
| } else if (source.IsRegister() && destination.IsStackSlot()) {
|
| - Exchange(source.reg(), destination.ToStackSlotAddress());
|
| + Exchange(source.reg(), Address::StackSlotAddress(destination));
|
| } else if (source.IsStackSlot() && destination.IsRegister()) {
|
| - Exchange(destination.reg(), source.ToStackSlotAddress());
|
| + Exchange(destination.reg(), Address::StackSlotAddress(source));
|
| } else if (source.IsStackSlot() && destination.IsStackSlot()) {
|
| - Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress());
|
| + Exchange(Address::StackSlotAddress(destination),
|
| + Address::StackSlotAddress(source));
|
| } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
|
| __ movaps(XMM0, source.fpu_reg());
|
| __ movaps(source.fpu_reg(), destination.fpu_reg());
|
| @@ -1808,8 +1809,8 @@
|
| XmmRegister reg = source.IsFpuRegister() ? source.fpu_reg()
|
| : destination.fpu_reg();
|
| Address slot_address = source.IsFpuRegister()
|
| - ? destination.ToStackSlotAddress()
|
| - : source.ToStackSlotAddress();
|
| + ? Address::StackSlotAddress(destination)
|
| + : Address::StackSlotAddress(source);
|
|
|
| if (double_width) {
|
| __ movsd(XMM0, slot_address);
|
| @@ -1820,8 +1821,9 @@
|
| }
|
| __ movaps(reg, XMM0);
|
| } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
|
| - const Address& source_slot_address = source.ToStackSlotAddress();
|
| - const Address& destination_slot_address = destination.ToStackSlotAddress();
|
| + const Address& source_slot_address = Address::StackSlotAddress(source);
|
| + const Address& destination_slot_address =
|
| + Address::StackSlotAddress(destination);
|
|
|
| ScratchFpuRegisterScope ensure_scratch(this, XMM0);
|
| __ movsd(XMM0, source_slot_address);
|
| @@ -1829,8 +1831,9 @@
|
| __ movsd(destination_slot_address, XMM0);
|
| __ movsd(source_slot_address, ensure_scratch.reg());
|
| } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
|
| - const Address& source_slot_address = source.ToStackSlotAddress();
|
| - const Address& destination_slot_address = destination.ToStackSlotAddress();
|
| + const Address& source_slot_address = Address::StackSlotAddress(source);
|
| + const Address& destination_slot_address =
|
| + Address::StackSlotAddress(destination);
|
|
|
| ScratchFpuRegisterScope ensure_scratch(this, XMM0);
|
| __ movups(XMM0, source_slot_address);
|
|
|