Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(27)

Side by Side Diff: runtime/vm/flow_graph_compiler_mips.cc

Issue 19464002: Replaces Location::ToStackSlotAddress() with Location::ToStackSlotOffset() (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 5 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
OLDNEW
1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS.
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/flow_graph_compiler.h" 8 #include "vm/flow_graph_compiler.h"
9 9
10 #include "lib/error.h" 10 #include "lib/error.h"
(...skipping 762 matching lines...) Expand 10 before | Expand all | Expand 10 after
773 __ LoadObject(T0, loc.constant()); 773 __ LoadObject(T0, loc.constant());
774 __ sw(T0, dest); 774 __ sw(T0, dest);
775 } else if (loc.IsRegister()) { 775 } else if (loc.IsRegister()) {
776 if (*push_emitted && loc.reg() == T0) { 776 if (*push_emitted && loc.reg() == T0) {
777 __ lw(T0, Address(SP, 0)); 777 __ lw(T0, Address(SP, 0));
778 __ sw(T0, dest); 778 __ sw(T0, dest);
779 } else { 779 } else {
780 __ sw(loc.reg(), dest); 780 __ sw(loc.reg(), dest);
781 } 781 }
782 } else { 782 } else {
783 Address src = loc.ToStackSlotAddress(); 783 const Address& src = Address::StackSlotAddress(loc);
784 if (!src.Equals(dest)) { 784 if (!src.Equals(dest)) {
785 if (!*push_emitted) { 785 if (!*push_emitted) {
786 __ Push(T0); 786 __ Push(T0);
787 *push_emitted = true; 787 *push_emitted = true;
788 } 788 }
789 __ lw(T0, src); 789 __ lw(T0, src);
790 __ sw(T0, dest); 790 __ sw(T0, dest);
791 } 791 }
792 } 792 }
793 } 793 }
(...skipping 1016 matching lines...) Expand 10 before | Expand all | Expand 10 after
1810 __ TraceSimMsg("ParallelMoveResolver::EmitMove"); 1810 __ TraceSimMsg("ParallelMoveResolver::EmitMove");
1811 MoveOperands* move = moves_[index]; 1811 MoveOperands* move = moves_[index];
1812 const Location source = move->src(); 1812 const Location source = move->src();
1813 const Location destination = move->dest(); 1813 const Location destination = move->dest();
1814 1814
1815 if (source.IsRegister()) { 1815 if (source.IsRegister()) {
1816 if (destination.IsRegister()) { 1816 if (destination.IsRegister()) {
1817 __ mov(destination.reg(), source.reg()); 1817 __ mov(destination.reg(), source.reg());
1818 } else { 1818 } else {
1819 ASSERT(destination.IsStackSlot()); 1819 ASSERT(destination.IsStackSlot());
1820 __ sw(source.reg(), destination.ToStackSlotAddress()); 1820 __ sw(source.reg(), Address::StackSlotAddress(destination));
1821 } 1821 }
1822 } else if (source.IsStackSlot()) { 1822 } else if (source.IsStackSlot()) {
1823 if (destination.IsRegister()) { 1823 if (destination.IsRegister()) {
1824 __ lw(destination.reg(), source.ToStackSlotAddress()); 1824 __ lw(destination.reg(), Address::StackSlotAddress(source));
1825 } else { 1825 } else {
1826 ASSERT(destination.IsStackSlot()); 1826 ASSERT(destination.IsStackSlot());
1827 MoveMemoryToMemory(destination.ToStackSlotAddress(), 1827 MoveMemoryToMemory(Address::StackSlotAddress(destination),
1828 source.ToStackSlotAddress()); 1828 Address::StackSlotAddress(source));
1829 } 1829 }
1830 } else if (source.IsFpuRegister()) { 1830 } else if (source.IsFpuRegister()) {
1831 if (destination.IsFpuRegister()) { 1831 if (destination.IsFpuRegister()) {
1832 __ movd(destination.fpu_reg(), source.fpu_reg()); 1832 __ movd(destination.fpu_reg(), source.fpu_reg());
1833 } else { 1833 } else {
1834 if (destination.IsDoubleStackSlot()) { 1834 if (destination.IsDoubleStackSlot()) {
1835 const Address& addr = destination.ToStackSlotAddress(); 1835 const Address& addr = Address::StackSlotAddress(destination);
1836 int32_t offset = addr.offset(); 1836 int32_t offset = addr.offset();
1837 __ StoreDToOffset(source.fpu_reg(), FP, offset); 1837 __ StoreDToOffset(source.fpu_reg(), FP, offset);
1838 } else { 1838 } else {
1839 ASSERT(destination.IsQuadStackSlot()); 1839 ASSERT(destination.IsQuadStackSlot());
1840 UNIMPLEMENTED(); 1840 UNIMPLEMENTED();
1841 } 1841 }
1842 } 1842 }
1843 } else if (source.IsDoubleStackSlot()) { 1843 } else if (source.IsDoubleStackSlot()) {
1844 if (destination.IsFpuRegister()) { 1844 if (destination.IsFpuRegister()) {
1845 const Address &addr = source.ToStackSlotAddress(); 1845 const Address &addr = Address::StackSlotAddress(source);
1846 const Register base = addr.base(); 1846 const Register base = addr.base();
1847 const int32_t offset = addr.offset(); 1847 const int32_t offset = addr.offset();
1848 __ LoadDFromOffset(destination.fpu_reg(), base, offset); 1848 __ LoadDFromOffset(destination.fpu_reg(), base, offset);
1849 } else { 1849 } else {
1850 ASSERT(destination.IsDoubleStackSlot()); 1850 ASSERT(destination.IsDoubleStackSlot());
1851 const Address& saddr = source.ToStackSlotAddress(); 1851 const Address& saddr = Address::StackSlotAddress(source);
1852 const Address& daddr = destination.ToStackSlotAddress(); 1852 const Address& daddr = Address::StackSlotAddress(destination);
1853 int32_t soffset = saddr.offset(); 1853 int32_t soffset = saddr.offset();
1854 int32_t doffset = daddr.offset(); 1854 int32_t doffset = daddr.offset();
1855 __ LoadDFromOffset(FpuTMP, FP, soffset); 1855 __ LoadDFromOffset(FpuTMP, FP, soffset);
1856 __ StoreDToOffset(FpuTMP, FP, doffset); 1856 __ StoreDToOffset(FpuTMP, FP, doffset);
1857 } 1857 }
1858 } else if (source.IsQuadStackSlot()) { 1858 } else if (source.IsQuadStackSlot()) {
1859 UNIMPLEMENTED(); 1859 UNIMPLEMENTED();
1860 } else { 1860 } else {
1861 ASSERT(source.IsConstant()); 1861 ASSERT(source.IsConstant());
1862 if (destination.IsRegister()) { 1862 if (destination.IsRegister()) {
1863 const Object& constant = source.constant(); 1863 const Object& constant = source.constant();
1864 __ LoadObject(destination.reg(), constant); 1864 __ LoadObject(destination.reg(), constant);
1865 } else { 1865 } else {
1866 ASSERT(destination.IsStackSlot()); 1866 ASSERT(destination.IsStackSlot());
1867 StoreObject(destination.ToStackSlotAddress(), source.constant()); 1867 StoreObject(Address::StackSlotAddress(destination), source.constant());
1868 } 1868 }
1869 } 1869 }
1870 1870
1871 move->Eliminate(); 1871 move->Eliminate();
1872 } 1872 }
1873 1873
1874 1874
1875 void ParallelMoveResolver::EmitSwap(int index) { 1875 void ParallelMoveResolver::EmitSwap(int index) {
1876 __ TraceSimMsg("ParallelMoveResolver::EmitSwap"); 1876 __ TraceSimMsg("ParallelMoveResolver::EmitSwap");
1877 MoveOperands* move = moves_[index]; 1877 MoveOperands* move = moves_[index];
1878 const Location source = move->src(); 1878 const Location source = move->src();
1879 const Location destination = move->dest(); 1879 const Location destination = move->dest();
1880 1880
1881 if (source.IsRegister() && destination.IsRegister()) { 1881 if (source.IsRegister() && destination.IsRegister()) {
1882 ASSERT(source.reg() != TMP1); 1882 ASSERT(source.reg() != TMP1);
1883 ASSERT(destination.reg() != TMP1); 1883 ASSERT(destination.reg() != TMP1);
1884 __ mov(TMP1, source.reg()); 1884 __ mov(TMP1, source.reg());
1885 __ mov(source.reg(), destination.reg()); 1885 __ mov(source.reg(), destination.reg());
1886 __ mov(destination.reg(), TMP1); 1886 __ mov(destination.reg(), TMP1);
1887 } else if (source.IsRegister() && destination.IsStackSlot()) { 1887 } else if (source.IsRegister() && destination.IsStackSlot()) {
1888 Exchange(source.reg(), destination.ToStackSlotAddress()); 1888 Exchange(source.reg(), Address::StackSlotAddress(destination));
1889 } else if (source.IsStackSlot() && destination.IsRegister()) { 1889 } else if (source.IsStackSlot() && destination.IsRegister()) {
1890 Exchange(destination.reg(), source.ToStackSlotAddress()); 1890 Exchange(destination.reg(), Address::StackSlotAddress(source));
1891 } else if (source.IsStackSlot() && destination.IsStackSlot()) { 1891 } else if (source.IsStackSlot() && destination.IsStackSlot()) {
1892 Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress()); 1892 Exchange(Address::StackSlotAddress(destination),
1893 Address::StackSlotAddress(source));
1893 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { 1894 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
1894 __ movd(FpuTMP, source.fpu_reg()); 1895 __ movd(FpuTMP, source.fpu_reg());
1895 __ movd(source.fpu_reg(), destination.fpu_reg()); 1896 __ movd(source.fpu_reg(), destination.fpu_reg());
1896 __ movd(destination.fpu_reg(), FpuTMP); 1897 __ movd(destination.fpu_reg(), FpuTMP);
1897 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { 1898 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
1898 ASSERT(destination.IsDoubleStackSlot() || 1899 ASSERT(destination.IsDoubleStackSlot() ||
1899 destination.IsQuadStackSlot() || 1900 destination.IsQuadStackSlot() ||
1900 source.IsDoubleStackSlot() || 1901 source.IsDoubleStackSlot() ||
1901 source.IsQuadStackSlot()); 1902 source.IsQuadStackSlot());
1902 bool double_width = destination.IsDoubleStackSlot() || 1903 bool double_width = destination.IsDoubleStackSlot() ||
1903 source.IsDoubleStackSlot(); 1904 source.IsDoubleStackSlot();
1904 DRegister reg = source.IsFpuRegister() ? source.fpu_reg() 1905 DRegister reg = source.IsFpuRegister() ? source.fpu_reg()
1905 : destination.fpu_reg(); 1906 : destination.fpu_reg();
1906 const Address& slot_address = source.IsFpuRegister() 1907 const Address& slot_address = source.IsFpuRegister()
1907 ? destination.ToStackSlotAddress() 1908 ? Address::StackSlotAddress(destination)
1908 : source.ToStackSlotAddress(); 1909 : Address::StackSlotAddress(source);
1909 1910
1910 if (double_width) { 1911 if (double_width) {
1911 const Register base = slot_address.base(); 1912 const Register base = slot_address.base();
1912 const int32_t offset = slot_address.offset(); 1913 const int32_t offset = slot_address.offset();
1913 __ LoadDFromOffset(FpuTMP, base, offset); 1914 __ LoadDFromOffset(FpuTMP, base, offset);
1914 __ StoreDToOffset(reg, base, offset); 1915 __ StoreDToOffset(reg, base, offset);
1915 __ movd(reg, FpuTMP); 1916 __ movd(reg, FpuTMP);
1916 } else { 1917 } else {
1917 UNIMPLEMENTED(); 1918 UNIMPLEMENTED();
1918 } 1919 }
1919 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { 1920 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
1920 const Address& source_slot_address = source.ToStackSlotAddress(); 1921 const Address& source_slot_address = Address::StackSlotAddress(source);
1921 const Address& destination_slot_address = destination.ToStackSlotAddress(); 1922 const Address& destination_slot_address =
1923 Address::StackSlotAddress(destination);
1922 const Register sbase = source_slot_address.base(); 1924 const Register sbase = source_slot_address.base();
1923 const int32_t soffset = source_slot_address.offset(); 1925 const int32_t soffset = source_slot_address.offset();
1924 const Register dbase = destination_slot_address.base(); 1926 const Register dbase = destination_slot_address.base();
1925 const int32_t doffset = destination_slot_address.offset(); 1927 const int32_t doffset = destination_slot_address.offset();
1926 1928
1927 ScratchFpuRegisterScope ensure_scratch(this, FpuTMP); 1929 ScratchFpuRegisterScope ensure_scratch(this, FpuTMP);
1928 __ LoadDFromOffset(FpuTMP, sbase, soffset); 1930 __ LoadDFromOffset(FpuTMP, sbase, soffset);
1929 __ LoadDFromOffset(ensure_scratch.reg(), dbase, doffset); 1931 __ LoadDFromOffset(ensure_scratch.reg(), dbase, doffset);
1930 __ StoreDToOffset(FpuTMP, dbase, doffset); 1932 __ StoreDToOffset(FpuTMP, dbase, doffset);
1931 __ StoreDToOffset(ensure_scratch.reg(), sbase, soffset); 1933 __ StoreDToOffset(ensure_scratch.reg(), sbase, soffset);
(...skipping 80 matching lines...) Expand 10 before | Expand all | Expand 10 after
2012 __ AddImmediate(SP, kDoubleSize); 2014 __ AddImmediate(SP, kDoubleSize);
2013 } 2015 }
2014 2016
2015 2017
2016 #undef __ 2018 #undef __
2017 2019
2018 2020
2019 } // namespace dart 2021 } // namespace dart
2020 2022
2021 #endif // defined TARGET_ARCH_MIPS 2023 #endif // defined TARGET_ARCH_MIPS
OLDNEW

Powered by Google App Engine
This is Rietveld 408576698