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Unified Diff: runtime/vm/simulator_arm.cc

Issue 1434323003: ARM: Don't generate memory instructions with writeback where the data and address registers are the… (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: Created 5 years, 1 month ago
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Index: runtime/vm/simulator_arm.cc
diff --git a/runtime/vm/simulator_arm.cc b/runtime/vm/simulator_arm.cc
index f3664d7e74fd29ee69e4d81e3bb91f00f297ebf4..74464c85688cccd91f22d983968e51c040c6e661 100644
--- a/runtime/vm/simulator_arm.cc
+++ b/runtime/vm/simulator_arm.cc
@@ -1996,6 +1996,7 @@ void Simulator::DecodeType01(Instr* instr) {
HandleIllegalAccess(addr, instr);
} else {
if (write_back) {
+ ASSERT(rd != rn); // Unpredictable.
set_register(rn, rn_val);
}
if (!instr->HasSign()) {
@@ -2312,6 +2313,7 @@ void Simulator::DecodeType2(Instr* instr) {
HandleIllegalAccess(addr, instr);
} else {
if (write_back) {
+ ASSERT(rd != rn); // Unpredictable.
set_register(rn, rn_val);
}
if (instr->HasB()) {
@@ -2424,6 +2426,7 @@ void Simulator::DecodeType3(Instr* instr) {
HandleIllegalAccess(addr, instr);
} else {
if (write_back) {
+ ASSERT(rd != rn); // Unpredictable.
set_register(rn, rn_val);
}
if (instr->HasB()) {

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