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Side by Side Diff: runtime/vm/simulator_arm.cc

Issue 1434323003: ARM: Don't generate memory instructions with writeback where the data and address registers are the… (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: Created 5 years, 1 month ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include <setjmp.h> // NOLINT 5 #include <setjmp.h> // NOLINT
6 #include <stdlib.h> 6 #include <stdlib.h>
7 7
8 #include "vm/globals.h" 8 #include "vm/globals.h"
9 #if defined(TARGET_ARCH_ARM) 9 #if defined(TARGET_ARCH_ARM)
10 10
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1989 // The PU field is a 2-bit field. 1989 // The PU field is a 2-bit field.
1990 UNREACHABLE(); 1990 UNREACHABLE();
1991 break; 1991 break;
1992 } 1992 }
1993 } 1993 }
1994 } 1994 }
1995 if (IsIllegalAddress(addr)) { 1995 if (IsIllegalAddress(addr)) {
1996 HandleIllegalAccess(addr, instr); 1996 HandleIllegalAccess(addr, instr);
1997 } else { 1997 } else {
1998 if (write_back) { 1998 if (write_back) {
1999 ASSERT(rd != rn); // Unpredictable.
1999 set_register(rn, rn_val); 2000 set_register(rn, rn_val);
2000 } 2001 }
2001 if (!instr->HasSign()) { 2002 if (!instr->HasSign()) {
2002 if (instr->HasL()) { 2003 if (instr->HasL()) {
2003 uint16_t val = ReadHU(addr, instr); 2004 uint16_t val = ReadHU(addr, instr);
2004 set_register(rd, val); 2005 set_register(rd, val);
2005 } else { 2006 } else {
2006 uint16_t val = get_register(rd); 2007 uint16_t val = get_register(rd);
2007 WriteH(addr, val, instr); 2008 WriteH(addr, val, instr);
2008 } 2009 }
(...skipping 296 matching lines...) Expand 10 before | Expand all | Expand 10 after
2305 } 2306 }
2306 default: { 2307 default: {
2307 UNREACHABLE(); 2308 UNREACHABLE();
2308 break; 2309 break;
2309 } 2310 }
2310 } 2311 }
2311 if (IsIllegalAddress(addr)) { 2312 if (IsIllegalAddress(addr)) {
2312 HandleIllegalAccess(addr, instr); 2313 HandleIllegalAccess(addr, instr);
2313 } else { 2314 } else {
2314 if (write_back) { 2315 if (write_back) {
2316 ASSERT(rd != rn); // Unpredictable.
2315 set_register(rn, rn_val); 2317 set_register(rn, rn_val);
2316 } 2318 }
2317 if (instr->HasB()) { 2319 if (instr->HasB()) {
2318 if (instr->HasL()) { 2320 if (instr->HasL()) {
2319 unsigned char val = ReadBU(addr); 2321 unsigned char val = ReadBU(addr);
2320 set_register(rd, val); 2322 set_register(rd, val);
2321 } else { 2323 } else {
2322 unsigned char val = get_register(rd); 2324 unsigned char val = get_register(rd);
2323 WriteB(addr, val); 2325 WriteB(addr, val);
2324 } 2326 }
(...skipping 92 matching lines...) Expand 10 before | Expand all | Expand 10 after
2417 } 2419 }
2418 default: { 2420 default: {
2419 UNREACHABLE(); 2421 UNREACHABLE();
2420 break; 2422 break;
2421 } 2423 }
2422 } 2424 }
2423 if (IsIllegalAddress(addr)) { 2425 if (IsIllegalAddress(addr)) {
2424 HandleIllegalAccess(addr, instr); 2426 HandleIllegalAccess(addr, instr);
2425 } else { 2427 } else {
2426 if (write_back) { 2428 if (write_back) {
2429 ASSERT(rd != rn); // Unpredictable.
2427 set_register(rn, rn_val); 2430 set_register(rn, rn_val);
2428 } 2431 }
2429 if (instr->HasB()) { 2432 if (instr->HasB()) {
2430 if (instr->HasL()) { 2433 if (instr->HasL()) {
2431 unsigned char val = ReadBU(addr); 2434 unsigned char val = ReadBU(addr);
2432 set_register(rd, val); 2435 set_register(rd, val);
2433 } else { 2436 } else {
2434 unsigned char val = get_register(rd); 2437 unsigned char val = get_register(rd);
2435 WriteB(addr, val); 2438 WriteB(addr, val);
2436 } 2439 }
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3883 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); 3886 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception));
3884 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); 3887 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace));
3885 buf->Longjmp(); 3888 buf->Longjmp();
3886 } 3889 }
3887 3890
3888 } // namespace dart 3891 } // namespace dart
3889 3892
3890 #endif // defined(USING_SIMULATOR) 3893 #endif // defined(USING_SIMULATOR)
3891 3894
3892 #endif // defined TARGET_ARCH_ARM 3895 #endif // defined TARGET_ARCH_ARM
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