Use generated actual decoders for ARM table:

src/trusted/validator_arm/gen/arm32_decode_baselines_2.cc

Index: src/trusted/validator_arm/gen/arm32_decode_baselines_2.cc
===================================================================
--- src/trusted/validator_arm/gen/arm32_decode_baselines_2.cc	(revision 10736)
+++ src/trusted/validator_arm/gen/arm32_decode_baselines_2.cc	(working copy)
@@ -900,6 +900,7 @@
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
@@ -921,8 +922,7 @@
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 Register STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ -975,8 +975,9 @@
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ -993,6 +994,7 @@
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
@@ -1014,8 +1016,7 @@
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 Register STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ -1068,8 +1069,9 @@
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ -1086,6 +1088,7 @@
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
@@ -1107,8 +1110,7 @@
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 Register STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ -1161,8 +1163,9 @@
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ -1179,6 +1182,7 @@
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
@@ -1200,8 +1204,7 @@
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 Register STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ -1254,8 +1257,9 @@
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0::