src/trusted/validator_arm/gen/arm32_decode_branch_branch_with_link_and_block_data_transfer_tests.cc - Issue 12223046: Use generated actual decoders for ARM table:

Unified Diff: src/trusted/validator_arm/gen/arm32_decode_branch_branch_with_link_and_block_data_transfer_tests.cc

Issue 12223046: Use generated actual decoders for ARM table: (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/

Patch Set: Created 7 years, 10 months ago

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Index: src/trusted/validator_arm/gen/arm32_decode_branch_branch_with_link_and_block_data_transfer_tests.cc

===================================================================

--- src/trusted/validator_arm/gen/arm32_decode_branch_branch_with_link_and_block_data_transfer_tests.cc (revision 10736)

+++ src/trusted/validator_arm/gen/arm32_decode_branch_branch_with_link_and_block_data_transfer_tests.cc (working copy)

@@ -39,7 +39,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -58,8 +58,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class LoadStoreRegisterListTesterCase0

@@ -128,7 +127,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -146,8 +145,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class LoadStoreRegisterListTesterCase1

@@ -216,7 +214,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -235,8 +233,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class LoadStoreRegisterListTesterCase2

@@ -305,7 +302,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -323,8 +320,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class LoadStoreRegisterListTesterCase3

@@ -393,7 +389,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -412,8 +408,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class LoadStoreRegisterListTesterCase4

@@ -482,7 +477,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -500,8 +495,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class LoadStoreRegisterListTesterCase5

@@ -570,7 +564,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -589,8 +583,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class LoadStoreRegisterListTesterCase6

@@ -659,7 +652,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -677,8 +670,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class LoadStoreRegisterListTesterCase7

@@ -843,7 +835,7 @@

// op(25:20)=10xxxx

// = {Pc: 15,

-// actual: BranchImmediate24,

+// actual: Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc},

@@ -852,7 +844,7 @@

// imm24: imm24(23:0),

// imm32: SignExtend(imm24:'00'(1:0), 32),

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// safety: [true => MAY_BE_SAFE],

// true: true,

// uses: {Pc}}

@@ -902,7 +894,7 @@

// op(25:20)=11xxxx

// = {Lr: 14,

// Pc: 15,

-// actual: BranchImmediate24,

+// actual: Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc, Lr},

@@ -911,7 +903,7 @@

// imm24: imm24(23:0),

// imm32: SignExtend(imm24:'00'(1:0), 32),

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// safety: [true => MAY_BE_SAFE],

// true: true,

// uses: {Pc}}

@@ -969,7 +961,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -989,8 +981,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class StoreRegisterListTester_Case0

@@ -1007,7 +998,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -1026,8 +1017,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class LoadRegisterListTester_Case1

@@ -1044,7 +1034,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -1064,8 +1054,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class StoreRegisterListTester_Case2

@@ -1082,7 +1071,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -1101,8 +1090,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class LoadRegisterListTester_Case3

@@ -1119,7 +1107,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -1139,8 +1127,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class StoreRegisterListTester_Case4

@@ -1157,7 +1144,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -1176,8 +1163,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class LoadRegisterListTester_Case5

@@ -1194,7 +1180,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -1214,8 +1200,7 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

class StoreRegisterListTester_Case6

@@ -1232,7 +1217,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -1251,8 +1236,7 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

class LoadRegisterListTester_Case7

@@ -1308,7 +1292,7 @@

// op(25:20)=10xxxx

// = {Pc: 15,

-// actual: BranchImmediate24,

+// actual: Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc},

@@ -1317,7 +1301,7 @@

// imm24: imm24(23:0),

// imm32: SignExtend(imm24:'00'(1:0), 32),

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// rule: B,

// safety: [true => MAY_BE_SAFE],

// true: true,

@@ -1334,7 +1318,7 @@

// op(25:20)=11xxxx

// = {Lr: 14,

// Pc: 15,

-// actual: BranchImmediate24,

+// actual: Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc, Lr},

@@ -1343,7 +1327,7 @@

// imm24: imm24(23:0),

// imm32: SignExtend(imm24:'00'(1:0), 32),

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// rule: BL_BLX_immediate,

// safety: [true => MAY_BE_SAFE],

// true: true,

@@ -1371,7 +1355,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -1392,14 +1376,15 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

TEST_F(Arm32DecoderStateTests,

StoreRegisterListTester_Case0_TestCase0) {

- StoreRegisterListTester_Case0 tester;

- tester.Test("cccc100000w0nnnnrrrrrrrrrrrrrrrr");

+ StoreRegisterListTester_Case0 baseline_tester;

+ NamedActual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1_STMDA_STMED actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc100000w0nnnnrrrrrrrrrrrrrrrr");

}

// op(25:20)=0000x1

@@ -1407,7 +1392,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -1427,14 +1412,15 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

TEST_F(Arm32DecoderStateTests,

LoadRegisterListTester_Case1_TestCase1) {

- LoadRegisterListTester_Case1 tester;

- tester.Test("cccc100000w1nnnnrrrrrrrrrrrrrrrr");

+ LoadRegisterListTester_Case1 baseline_tester;

+ NamedActual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1_LDMDA_LDMFA actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc100000w1nnnnrrrrrrrrrrrrrrrr");

}

// op(25:20)=0010x0

@@ -1442,7 +1428,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -1463,14 +1449,15 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

TEST_F(Arm32DecoderStateTests,

StoreRegisterListTester_Case2_TestCase2) {

- StoreRegisterListTester_Case2 tester;

- tester.Test("cccc100010w0nnnnrrrrrrrrrrrrrrrr");

+ StoreRegisterListTester_Case2 baseline_tester;

+ NamedActual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1_STM_STMIA_STMEA actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc100010w0nnnnrrrrrrrrrrrrrrrr");

}

// op(25:20)=0010x1

@@ -1478,7 +1465,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -1498,14 +1485,15 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

TEST_F(Arm32DecoderStateTests,

LoadRegisterListTester_Case3_TestCase3) {

- LoadRegisterListTester_Case3 tester;

- tester.Test("cccc100010w1nnnnrrrrrrrrrrrrrrrr");

+ LoadRegisterListTester_Case3 baseline_tester;

+ NamedActual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1_LDM_LDMIA_LDMFD actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc100010w1nnnnrrrrrrrrrrrrrrrr");

}

// op(25:20)=0100x0

@@ -1513,7 +1501,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -1534,14 +1522,15 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

TEST_F(Arm32DecoderStateTests,

StoreRegisterListTester_Case4_TestCase4) {

- StoreRegisterListTester_Case4 tester;

- tester.Test("cccc100100w0nnnnrrrrrrrrrrrrrrrr");

+ StoreRegisterListTester_Case4 baseline_tester;

+ NamedActual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1_STMDB_STMFD actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc100100w0nnnnrrrrrrrrrrrrrrrr");

}

// op(25:20)=0100x1

@@ -1549,7 +1538,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -1569,14 +1558,15 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

TEST_F(Arm32DecoderStateTests,

LoadRegisterListTester_Case5_TestCase5) {

- LoadRegisterListTester_Case5 tester;

- tester.Test("cccc100100w1nnnnrrrrrrrrrrrrrrrr");

+ LoadRegisterListTester_Case5 baseline_tester;

+ NamedActual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1_LDMDB_LDMEA actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc100100w1nnnnrrrrrrrrrrrrrrrr");

}

// op(25:20)=0110x0

@@ -1584,7 +1574,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: StoreRegisterList,

+// actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: StoreRegisterList,

// constraints: ,

@@ -1605,14 +1595,15 @@

// Contains(registers, Rn) &&

// Rn !=

// SmallestGPR(registers) => UNKNOWN],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: Union({Rn}, registers),

// wback: W(21)=1}

TEST_F(Arm32DecoderStateTests,

StoreRegisterListTester_Case6_TestCase6) {

- StoreRegisterListTester_Case6 tester;

- tester.Test("cccc100110w0nnnnrrrrrrrrrrrrrrrr");

+ StoreRegisterListTester_Case6 baseline_tester;

+ NamedActual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1_STMIB_STMFA actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc100110w0nnnnrrrrrrrrrrrrrrrr");

}

// op(25:20)=0110x1

@@ -1620,7 +1611,7 @@

// Pc: 15,

// Rn: Rn(19:16),

// W: W(21),

-// actual: LoadRegisterList,

+// actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,

// base: Rn,

// baseline: LoadRegisterList,

// constraints: ,

@@ -1640,14 +1631,15 @@

// wback &&

// Contains(registers, Rn) => UNKNOWN,

// Contains(registers, Pc) => FORBIDDEN_OPERANDS],

-// small_imm_base_wb: true,

-// true: true,

+// small_imm_base_wb: wback,

// uses: {Rn},

// wback: W(21)=1}

TEST_F(Arm32DecoderStateTests,

LoadRegisterListTester_Case7_TestCase7) {

- LoadRegisterListTester_Case7 tester;

- tester.Test("cccc100110w1nnnnrrrrrrrrrrrrrrrr");

+ LoadRegisterListTester_Case7 baseline_tester;

+ NamedActual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1_LDMIB_LDMED actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc100110w1nnnnrrrrrrrrrrrrrrrr");

}

// op(25:20)=0xx1x0 & $pattern(31:0)=xxxxxxxxxx0xxxxxxxxxxxxxxxxxxxxx

@@ -1688,7 +1680,7 @@

// op(25:20)=10xxxx

// = {Pc: 15,

-// actual: BranchImmediate24,

+// actual: Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc},

@@ -1698,21 +1690,23 @@

// imm32: SignExtend(imm24:'00'(1:0), 32),

// pattern: cccc1010iiiiiiiiiiiiiiiiiiiiiiii,

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// rule: B,

// safety: [true => MAY_BE_SAFE],

// true: true,

// uses: {Pc}}

TEST_F(Arm32DecoderStateTests,

BranchImmediate24Tester_Case11_TestCase11) {

- BranchImmediate24Tester_Case11 tester;

- tester.Test("cccc1010iiiiiiiiiiiiiiiiiiiiiiii");

+ BranchImmediate24Tester_Case11 baseline_tester;

+ NamedActual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1_B actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc1010iiiiiiiiiiiiiiiiiiiiiiii");

}

// op(25:20)=11xxxx

// = {Lr: 14,

// Pc: 15,

-// actual: BranchImmediate24,

+// actual: Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1,

// baseline: BranchImmediate24,

// constraints: ,

// defs: {Pc, Lr},

@@ -1722,15 +1716,17 @@

// imm32: SignExtend(imm24:'00'(1:0), 32),

// pattern: cccc1011iiiiiiiiiiiiiiiiiiiiiiii,

// relative: true,

-// relative_offset: imm32,

+// relative_offset: imm32 + 8,

// rule: BL_BLX_immediate,

// safety: [true => MAY_BE_SAFE],

// true: true,

// uses: {Pc}}

TEST_F(Arm32DecoderStateTests,

BranchImmediate24Tester_Case12_TestCase12) {

- BranchImmediate24Tester_Case12 tester;

- tester.Test("cccc1011iiiiiiiiiiiiiiiiiiiiiiii");

+ BranchImmediate24Tester_Case12 baseline_tester;

+ NamedActual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1_BL_BLX_immediate actual;

+ ActualVsBaselineTester a_vs_b_tester(actual, baseline_tester);

+ a_vs_b_tester.Test("cccc1011iiiiiiiiiiiiiiiiiiiiiiii");

}

} // namespace nacl_arm_test