Use generated actual decoders for ARM table:

src/trusted/validator_arm/gen/arm32_decode_baselines_2.cc

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #include "native_client/src/trusted/validator_arm/gen/arm32_decode_baselines.h"
 #include "native_client/src/trusted/validator_arm/inst_classes.h"
@@ skipping 882 matching lines @@
   // uses: '{}'
   return RegisterList();
 }
 
 // STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: {Rn
 //         if wback
 //         else None},
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100000w0nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: STMDA_STMED,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 Register STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ skipping 32 matching lines @@
     return UNKNOWN;
 
   return MAY_BE_SAFE;
 }
 
 
 bool STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: 'Union({inst(19:16)}, RegisterList(inst(15:0)))'
   return nacl_arm_dec::Union(RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
 }
 
 // STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: {Rn
 //         if wback
 //         else None},
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100100w0nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: STMDB_STMFD,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 Register STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ skipping 32 matching lines @@
     return UNKNOWN;
 
   return MAY_BE_SAFE;
 }
 
 
 bool STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList STMDB_STMFD_cccc100100w0nnnnrrrrrrrrrrrrrrrr_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: 'Union({inst(19:16)}, RegisterList(inst(15:0)))'
   return nacl_arm_dec::Union(RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
 }
 
 // STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: {Rn
 //         if wback
 //         else None},
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100110w0nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: STMIB_STMFA,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 Register STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ skipping 32 matching lines @@
     return UNKNOWN;
 
   return MAY_BE_SAFE;
 }
 
 
 bool STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList STMIB_STMFA_cccc100110w0nnnnrrrrrrrrrrrrrrrr_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: 'Union({inst(19:16)}, RegisterList(inst(15:0)))'
   return nacl_arm_dec::Union(RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
 }
 
 // STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_STMDA_STMED_cccc100000w0nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: StoreRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: {Rn
 //         if wback
 //         else None},
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100010w0nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: STM_STMIA_STMEA,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) &&
 //         Rn  !=
 //            SmallestGPR(registers) => UNKNOWN],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: Union({Rn}, registers),
 //    wback: W(21)=1}
 Register STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // base: 'inst(19:16)'
   return Register(((inst.Bits() & 0x000F0000) >> 16));
 }
 
 RegisterList STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0::
@@ skipping 32 matching lines @@
     return UNKNOWN;
 
   return MAY_BE_SAFE;
 }
 
 
 bool STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0::
 base_address_register_writeback_small_immediate(
       Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
-  // small_imm_base_wb: 'true'
-  return true;
+  // small_imm_base_wb: 'inst(21)=1'
+  return (inst.Bits() & 0x00200000)  ==
+          0x00200000;
 }
 
 RegisterList STM_STMIA_STMEA_cccc100010w0nnnnrrrrrrrrrrrrrrrr_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: 'Union({inst(19:16)}, RegisterList(inst(15:0)))'
   return nacl_arm_dec::Union(RegisterList().
    Add(Register(((inst.Bits() & 0x000F0000) >> 16))), nacl_arm_dec::RegisterList((inst.Bits() & 0x0000FFFF)));
 }
 
@@ skipping 9086 matching lines @@
 
 
 RegisterList VHSUB_1111001u0dssnnnndddd0010nqm0mmmm_case_0::
 uses(Instruction inst) const {
   UNREFERENCED_PARAMETER(inst);  // To silence compiler.
   // uses: '{}'
   return RegisterList();
 }
 
 }  // namespace nacl_arm_dec