Fixes for ARM/ARM64/MIPS parallel move resolver.

Fixes for ARM/ARM64/MIPS parallel move resolver.

The parallel move resolve has to block reserved registers like
TMP, TMP2, PP, CTX so that they are not used as scratch registers.

Use allocated scratch register instead of IP because IP may be
used for large stack slot offsets.

This CL also generalizes stack-slot locations to address
stack lots relative to FP or SP.

R=zra@google.com

Committed: https://code.google.com/p/dart/source/detail?r=39905

[Florian Schneider, 2014-09-04 12:54:07]

fschneider@google.com changed reviewers:
+ zra@google.com

[zra, 2014-09-04 16:05:39]

lgtm with questions.

Thanks for doing this!

https://codereview.chromium.org/539073002/diff/1/runtime/vm/flow_graph_compil...
File runtime/vm/flow_graph_compiler_arm.cc (right):

https://codereview.chromium.org/539073002/diff/1/runtime/vm/flow_graph_compil...
runtime/vm/flow_graph_compiler_arm.cc:1664: Register base_reg =
source.IsFpuRegister()
Not sure I follow what's going on here. Is there an assumption being made that
I'm missing that could be wrapped up in an assert?

https://codereview.chromium.org/539073002/diff/1/runtime/vm/locations.h
File runtime/vm/locations.h (right):

https://codereview.chromium.org/539073002/diff/1/runtime/vm/locations.h#newco...
runtime/vm/locations.h:390: static const intptr_t kBitsForBaseReg = 5;
It looks like the base reg can only ever be FPREG or SPREG. Not sure if it makes
sense to encode this differently. Thoughts?

[Florian Schneider, 2014-09-04 16:17:24]

https://codereview.chromium.org/539073002/diff/1/runtime/vm/flow_graph_compil...
File runtime/vm/flow_graph_compiler_arm.cc (right):

https://codereview.chromium.org/539073002/diff/1/runtime/vm/flow_graph_compil...
runtime/vm/flow_graph_compiler_arm.cc:1664: Register base_reg =
source.IsFpuRegister()
On 2014/09/04 16:05:38, zra wrote:
> Not sure I follow what's going on here. Is there an assumption being made that
> I'm missing that could be wrapped up in an assert?

This is just the case of FpuRegister/DoubleStackSlot or
FpuRegister/QuadStackSlot.

If one of source/destination is FpuRegister, the other one is the stack slot
since the FpuRegister/FpuRegister case is handled above.

https://codereview.chromium.org/539073002/diff/1/runtime/vm/locations.h
File runtime/vm/locations.h (right):

https://codereview.chromium.org/539073002/diff/1/runtime/vm/locations.h#newco...
runtime/vm/locations.h:390: static const intptr_t kBitsForBaseReg = 5;
On 2014/09/04 16:05:39, zra wrote:
> It looks like the base reg can only ever be FPREG or SPREG. Not sure if it
makes
> sense to encode this differently. Thoughts?

It seems the most straight-forward to encode the register directly, and 5 bits
(32 registers) is the maximum needed for all platforms, but it leaves only 23
bits for the index on ia32.

But yes, for this 1 bit would be enough. Not sure if it is worth to change it
for now.

[Florian Schneider, 2014-09-05 09:50:03]

Committed patchset #1 (id:1) manually as r39905 (presubmit successful).