Fixes for ARM/ARM64/MIPS parallel move resolver.

runtime/vm/flow_graph_compiler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/flow_graph_compiler.h"
 
 #include "vm/ast_printer.h"
@@ skipping 1497 matching lines @@
   MoveOperands* move = moves_[index];
   const Location source = move->src();
   const Location destination = move->dest();
 
   if (source.IsRegister()) {
     if (destination.IsRegister()) {
       __ mov(destination.reg(), Operand(source.reg()));
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      __ StoreToOffset(kWord, source.reg(), FP, dest_offset);
+      __ StoreToOffset(
+          kWord, source.reg(), destination.base_reg(), dest_offset);
     }
   } else if (source.IsStackSlot()) {
     if (destination.IsRegister()) {
       const intptr_t source_offset = source.ToStackSlotOffset();
-      __ LoadFromOffset(kWord, destination.reg(), FP, source_offset);
+      __ LoadFromOffset(
+          kWord, destination.reg(), source.base_reg(), source_offset);
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      __ LoadFromOffset(kWord, TMP, FP, source_offset);
-      __ StoreToOffset(kWord, TMP, FP, dest_offset);
+      __ LoadFromOffset(kWord, TMP, source.base_reg(), source_offset);
+      __ StoreToOffset(kWord, TMP, destination.base_reg(), dest_offset);
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
       if (TargetCPUFeatures::neon_supported()) {
         __ vmovq(destination.fpu_reg(), source.fpu_reg());
       } else {
         // If we're not inlining simd values, then only the even numbered D
         // register will have anything in them.
         __ vmovd(EvenDRegisterOf(destination.fpu_reg()),
                  EvenDRegisterOf(source.fpu_reg()));
       }
     } else {
       if (destination.IsDoubleStackSlot()) {
         const intptr_t dest_offset = destination.ToStackSlotOffset();
         DRegister src = EvenDRegisterOf(source.fpu_reg());
-        __ StoreDToOffset(src, FP, dest_offset);
+        __ StoreDToOffset(src, destination.base_reg(), dest_offset);
       } else {
         ASSERT(destination.IsQuadStackSlot());
         const intptr_t dest_offset = destination.ToStackSlotOffset();
         const DRegister dsrc0 = EvenDRegisterOf(source.fpu_reg());
-        __ StoreMultipleDToOffset(dsrc0, 2, FP, dest_offset);
+        __ StoreMultipleDToOffset(
+            dsrc0, 2, destination.base_reg(), dest_offset);
       }
     }
   } else if (source.IsDoubleStackSlot()) {
     if (destination.IsFpuRegister()) {
-      const intptr_t dest_offset = source.ToStackSlotOffset();
+      const intptr_t source_offset = source.ToStackSlotOffset();
       const DRegister dst = EvenDRegisterOf(destination.fpu_reg());
-      __ LoadDFromOffset(dst, FP, dest_offset);
+      __ LoadDFromOffset(dst, source.base_reg(), source_offset);
     } else {
       ASSERT(destination.IsDoubleStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      __ LoadDFromOffset(DTMP, FP, source_offset);
-      __ StoreDToOffset(DTMP, FP, dest_offset);
+      __ LoadDFromOffset(DTMP, source.base_reg(), source_offset);
+      __ StoreDToOffset(DTMP, destination.base_reg(), dest_offset);
     }
   } else if (source.IsQuadStackSlot()) {
     if (destination.IsFpuRegister()) {
-      const intptr_t dest_offset = source.ToStackSlotOffset();
+      const intptr_t source_offset = source.ToStackSlotOffset();
       const DRegister dst0 = EvenDRegisterOf(destination.fpu_reg());
-      __ LoadMultipleDFromOffset(dst0, 2, FP, dest_offset);
+      __ LoadMultipleDFromOffset(dst0, 2, source.base_reg(), source_offset);
     } else {
       ASSERT(destination.IsQuadStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
       const DRegister dtmp0 = DTMP;
-      __ LoadMultipleDFromOffset(dtmp0, 2, FP, source_offset);
-      __ StoreMultipleDToOffset(dtmp0, 2, FP, dest_offset);
+      __ LoadMultipleDFromOffset(dtmp0, 2, source.base_reg(), source_offset);
+      __ StoreMultipleDToOffset(dtmp0, 2, destination.base_reg(), dest_offset);
     }
   } else {
     ASSERT(source.IsConstant());
     const Object& constant = source.constant();
     if (destination.IsRegister()) {
       if (source.constant_instruction()->representation() == kUnboxedInt32) {
         __ LoadImmediate(destination.reg(), Smi::Cast(constant).Value());
       } else {
         __ LoadObject(destination.reg(), constant);
       }
@@ skipping 11 matching lines @@
     } else if (destination.IsDoubleStackSlot()) {
       if (Utils::DoublesBitEqual(Double::Cast(constant).value(), 0.0) &&
           TargetCPUFeatures::neon_supported()) {
         __ veorq(QTMP, QTMP, QTMP);
       } else {
         __ LoadObject(TMP, constant);
         __ AddImmediate(TMP, TMP, Double::value_offset() - kHeapObjectTag);
         __ vldrd(DTMP, Address(TMP, 0));
       }
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      __ StoreDToOffset(DTMP, FP, dest_offset);
+      __ StoreDToOffset(DTMP, destination.base_reg(), dest_offset);
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t dest_offset = destination.ToStackSlotOffset();
       if (source.constant_instruction()->representation() == kUnboxedInt32) {
         __ LoadImmediate(TMP, Smi::Cast(constant).Value());
       } else {
         __ LoadObject(TMP, constant);
       }
-      __ StoreToOffset(kWord, TMP, FP, dest_offset);
+      __ StoreToOffset(kWord, TMP, destination.base_reg(), dest_offset);
     }
   }
 
   move->Eliminate();
 }
 
 
 void ParallelMoveResolver::EmitSwap(int index) {
   MoveOperands* move = moves_[index];
   const Location source = move->src();
   const Location destination = move->dest();
 
   if (source.IsRegister() && destination.IsRegister()) {
     ASSERT(source.reg() != IP);
     ASSERT(destination.reg() != IP);
     __ mov(IP, Operand(source.reg()));
     __ mov(source.reg(), Operand(destination.reg()));
     __ mov(destination.reg(), Operand(IP));
   } else if (source.IsRegister() && destination.IsStackSlot()) {
-    Exchange(source.reg(), destination.ToStackSlotOffset());
+    Exchange(source.reg(),
+             destination.base_reg(), destination.ToStackSlotOffset());
   } else if (source.IsStackSlot() && destination.IsRegister()) {
-    Exchange(destination.reg(), source.ToStackSlotOffset());
+    Exchange(destination.reg(),
+             source.base_reg(), source.ToStackSlotOffset());
   } else if (source.IsStackSlot() && destination.IsStackSlot()) {
-    Exchange(source.ToStackSlotOffset(), destination.ToStackSlotOffset());
+    Exchange(source.base_reg(), source.ToStackSlotOffset(),
+             destination.base_reg(), destination.ToStackSlotOffset());
   } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
     const DRegister dst = EvenDRegisterOf(destination.fpu_reg());
     DRegister src = EvenDRegisterOf(source.fpu_reg());
     __ vmovd(DTMP, src);
     __ vmovd(src, dst);
     __ vmovd(dst, DTMP);
   } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
     ASSERT(destination.IsDoubleStackSlot() ||
            destination.IsQuadStackSlot() ||
            source.IsDoubleStackSlot() ||
            source.IsQuadStackSlot());
     bool double_width = destination.IsDoubleStackSlot() ||
                         source.IsDoubleStackSlot();
     QRegister qreg = source.IsFpuRegister() ? source.fpu_reg()
                                             : destination.fpu_reg();
     DRegister reg = EvenDRegisterOf(qreg);
+    Register base_reg = source.IsFpuRegister()

[zra, 2014/09/04 16:05:38]

Not sure I follow what's going on here. Is there an assumption being made that
I'm missing that could be wrapped up in an assert?

[Florian Schneider, 2014/09/04 16:17:24]

This is just the case of FpuRegister/DoubleStackSlot or
FpuRegister/QuadStackSlot.

If one of source/destination is FpuRegister, the other one is the stack slot
since the FpuRegister/FpuRegister case is handled above.

+        ? destination.base_reg()
+        : source.base_reg();
     const intptr_t slot_offset = source.IsFpuRegister()
         ? destination.ToStackSlotOffset()
         : source.ToStackSlotOffset();
 
     if (double_width) {
-      __ LoadDFromOffset(DTMP, FP, slot_offset);
-      __ StoreDToOffset(reg, FP, slot_offset);
+      __ LoadDFromOffset(DTMP, base_reg, slot_offset);
+      __ StoreDToOffset(reg, base_reg, slot_offset);
       __ vmovd(reg, DTMP);
     } else {
-      UNIMPLEMENTED();
+      __ LoadMultipleDFromOffset(DTMP, 2, base_reg, slot_offset);
+      __ StoreMultipleDToOffset(reg, 2, base_reg, slot_offset);
+      __ vmovq(qreg, QTMP);
     }
   } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
     const intptr_t source_offset = source.ToStackSlotOffset();
     const intptr_t dest_offset = destination.ToStackSlotOffset();
 
-    ScratchFpuRegisterScope ensure_scratch(this, QTMP);
+    ScratchFpuRegisterScope ensure_scratch(this, kNoQRegister);
     DRegister scratch = EvenDRegisterOf(ensure_scratch.reg());
-    __ LoadDFromOffset(DTMP, FP, source_offset);
-    __ LoadDFromOffset(scratch, FP, dest_offset);
-    __ StoreDToOffset(DTMP, FP, dest_offset);
-    __ StoreDToOffset(scratch, FP, source_offset);
+    __ LoadDFromOffset(DTMP, source.base_reg(), source_offset);
+    __ LoadDFromOffset(scratch, destination.base_reg(), dest_offset);
+    __ StoreDToOffset(DTMP, destination.base_reg(), dest_offset);
+    __ StoreDToOffset(scratch, destination.base_reg(), source_offset);
   } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
-    UNIMPLEMENTED();
+    const intptr_t source_offset = source.ToStackSlotOffset();
+    const intptr_t dest_offset = destination.ToStackSlotOffset();
+
+    ScratchFpuRegisterScope ensure_scratch(this, kNoQRegister);
+    DRegister scratch = EvenDRegisterOf(ensure_scratch.reg());
+    __ LoadMultipleDFromOffset(DTMP, 2, source.base_reg(), source_offset);
+    __ LoadMultipleDFromOffset(scratch, 2, destination.base_reg(), dest_offset);
+    __ StoreMultipleDToOffset(DTMP, 2, destination.base_reg(), dest_offset);
+    __ StoreMultipleDToOffset(
+        scratch, 2, destination.base_reg(), source_offset);
   } else {
     UNREACHABLE();
   }
 
   // The swap of source and destination has executed a move from source to
   // destination.
   move->Eliminate();
 
   // Any unperformed (including pending) move with a source of either
   // this move's source or destination needs to have their source
   // changed to reflect the state of affairs after the swap.
   for (int i = 0; i < moves_.length(); ++i) {
     const MoveOperands& other_move = *moves_[i];
     if (other_move.Blocks(source)) {
       moves_[i]->set_src(destination);
     } else if (other_move.Blocks(destination)) {
       moves_[i]->set_src(source);
     }
   }
 }
 
 
 void ParallelMoveResolver::MoveMemoryToMemory(const Address& dst,
                                               const Address& src) {
-  __ ldr(IP, src);
-  __ str(IP, dst);
+  UNREACHABLE();
 }
 
 
 void ParallelMoveResolver::StoreObject(const Address& dst, const Object& obj) {
-  __ LoadObject(IP, obj);
-  __ str(IP, dst);
+  UNREACHABLE();
 }
 
 
 // Do not call or implement this function. Instead, use the form below that
 // uses an offset from the frame pointer instead of an Address.
 void ParallelMoveResolver::Exchange(Register reg, const Address& mem) {
   UNREACHABLE();
 }
 
 
 // Do not call or implement this function. Instead, use the form below that
 // uses offsets from the frame pointer instead of Addresses.
 void ParallelMoveResolver::Exchange(const Address& mem1, const Address& mem2) {
   UNREACHABLE();
 }
 
 
-void ParallelMoveResolver::Exchange(Register reg, intptr_t stack_offset) {
-  __ mov(TMP, Operand(reg));
-  __ LoadFromOffset(kWord, reg, FP, stack_offset);
-  __ StoreToOffset(kWord, TMP, FP, stack_offset);
+void ParallelMoveResolver::Exchange(Register reg,
+                                    Register base_reg,
+                                    intptr_t stack_offset) {
+  ScratchRegisterScope tmp(this, reg);
+  __ mov(tmp.reg(), Operand(reg));
+  __ LoadFromOffset(kWord, reg, base_reg, stack_offset);
+  __ StoreToOffset(kWord, tmp.reg(), base_reg, stack_offset);
 }
 
 
-void ParallelMoveResolver::Exchange(intptr_t stack_offset1,
+void ParallelMoveResolver::Exchange(Register base_reg1,
+                                    intptr_t stack_offset1,
+                                    Register base_reg2,
                                     intptr_t stack_offset2) {
-  ScratchRegisterScope ensure_scratch(this, IP);
-  __ LoadFromOffset(kWord, ensure_scratch.reg(), FP, stack_offset1);
-  __ LoadFromOffset(kWord, TMP, FP, stack_offset2);
-  __ StoreToOffset(kWord, ensure_scratch.reg(), FP, stack_offset2);
-  __ StoreToOffset(kWord, TMP, FP, stack_offset1);
+  ScratchRegisterScope tmp1(this, kNoRegister);
+  ScratchRegisterScope tmp2(this, tmp1.reg());
+  __ LoadFromOffset(kWord, tmp1.reg(), base_reg1, stack_offset1);
+  __ LoadFromOffset(kWord, tmp2.reg(), base_reg2, stack_offset2);
+  __ StoreToOffset(kWord, tmp1.reg(), base_reg2, stack_offset2);
+  __ StoreToOffset(kWord, tmp2.reg(), base_reg1, stack_offset1);
 }
 
 
 void ParallelMoveResolver::SpillScratch(Register reg) {
   __ Push(reg);
 }
 
 
 void ParallelMoveResolver::RestoreScratch(Register reg) {
   __ Pop(reg);
@@ skipping 10 matching lines @@
   DRegister dreg = EvenDRegisterOf(reg);
   __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex));
 }
 
 
 #undef __
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM