DescriptionCHROMIUM: video: tegra: Run pll_d at 252mhz for HDMI 640x480
Using a pll_d clock rate of 216MHz yields a 24MHz pixel clock instead of
25.2MHz. This is just under a 5% error. Instead, use a 252MHz pll_d rate,
which generates 25.2MHz exactly.
This makes it more likely that monitors will sync to the emitted signal.
This also fixes HDMI audio issues, since the CTS/N tables are now based
on the actual pixel clock rate, not merely the intended pixel clock rate.
Tested with a 12MHz pll_m rate on Seaboard, all of 32/44.1/48KHz audio,
all video modes supported by the Tegra dc HDMI driver, and a Dell U2410
dislay.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
BUG=
TEST=
Patch Set 1 #
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