MIPS: [turbofan] Support for %_DoubleHi, %_DoubleLo and %_ConstructDouble.

MIPS: [turbofan] Support for %_DoubleHi, %_DoubleLo and %_ConstructDouble.

Port 4436c2642a9b7adc9a1b68577ae9ca9a9a404c06

Original commit message:
This adds support for the double bits intrinsics to TurboFan, and is
a first step towards fast Math functions inlined into TurboFan code
or even compiled by themselves with TurboFan.

BUG=

Committed: https://crrev.com/b9ed2199bdff292bfdf49fb3d05eb3564ece27bd
Cr-Commit-Position: refs/heads/master@{#27028}

[balazs.kilvady, 2015-03-05 14:35:03]

balazs.kilvady@imgtec.com changed reviewers:
+ akos.palfi@imgtec.com, dusan.milosavljevic@imgtec.com, gergely.kis@imgtec.com,
paul.lind@imgtec.com

[balazs.kilvady, 2015-03-05 14:35:50]

balazs.kilvady@imgtec.com changed reviewers:
+ bmeurer@chromium.org, danno@chromium.org

[balazs.kilvady, 2015-03-05 14:45:58]

PTAL

In src/compiler/mips*/code-generator-mips*.cc I used a
    case kMips64FmoveLowDUw:
      __ mfhc1(at, i.OutputDoubleRegister());
      __ FmoveLow(i.OutputDoubleRegister(), i.InputRegister(1));
      __ mthc1(at, i.OutputDoubleRegister());
implementation to save the upper part of the FP register (needed by
cctes/test-run-machop/RunFloat64InsertLowWord32). That safety code could also be
moved to macro-assembler or to src/compiler/mips*/instruction-selector-mips*.cc.
On mips32 we need this code only if fp64 mode is used.

[dusmil.imgtec, 2015-03-05 14:58:21]

https://codereview.chromium.org/980073003/diff/1/src/compiler/mips/code-gener...
File src/compiler/mips/code-generator-mips.cc (right):

https://codereview.chromium.org/980073003/diff/1/src/compiler/mips/code-gener...
src/compiler/mips/code-generator-mips.cc:628: if
(CpuFeatures::IsSupported(FP64FPU)) {
The selection is not good, you forced runtime checks.
Use macro version for moves which hides fpu mode selection.

[balazs.kilvady, 2015-03-05 17:25:55]

https://codereview.chromium.org/980073003/diff/1/src/compiler/mips/code-gener...
File src/compiler/mips/code-generator-mips.cc (right):

https://codereview.chromium.org/980073003/diff/1/src/compiler/mips/code-gener...
src/compiler/mips/code-generator-mips.cc:628: if
(CpuFeatures::IsSupported(FP64FPU)) {
On 2015/03/05 14:58:21, dusmil.imgtec wrote:
> The selection is not good, you forced runtime checks.
> Use macro version for moves which hides fpu mode selection.

Done.

[paul.l..., 2015-03-05 17:40:48]

one drive-by comment

https://codereview.chromium.org/980073003/diff/20001/src/compiler/mips64/code...
File src/compiler/mips64/code-generator-mips64.cc (right):

https://codereview.chromium.org/980073003/diff/20001/src/compiler/mips64/code...
src/compiler/mips64/code-generator-mips64.cc:693: __ dsrlv(i.OutputRegister(),
i.OutputRegister(), at);
You can avoid the load and use of 'at' register here by using:
__ dsll32(i.OutputRegister(), i.OutputRegister(), 0);
__ dsrl32(i.OutputRegister(), i.OutputRegister(), 0);

[balazs.kilvady, 2015-03-05 18:07:08]

https://codereview.chromium.org/980073003/diff/20001/src/compiler/mips64/code...
File src/compiler/mips64/code-generator-mips64.cc (right):

https://codereview.chromium.org/980073003/diff/20001/src/compiler/mips64/code...
src/compiler/mips64/code-generator-mips64.cc:693: __ dsrlv(i.OutputRegister(),
i.OutputRegister(), at);
On 2015/03/05 17:40:48, paul.l... wrote:
> You can avoid the load and use of 'at' register here by using:
> __ dsll32(i.OutputRegister(), i.OutputRegister(), 0);
> __ dsrl32(i.OutputRegister(), i.OutputRegister(), 0);

Thanks, I modify it. Anyway test are passed without the 2 shifts I just added
them to ensure unsigned result. Could I drop it?

[paul.l..., 2015-03-05 18:43:49]

LGTM

https://codereview.chromium.org/980073003/diff/20001/src/compiler/mips64/code...
File src/compiler/mips64/code-generator-mips64.cc (right):

https://codereview.chromium.org/980073003/diff/20001/src/compiler/mips64/code...
src/compiler/mips64/code-generator-mips64.cc:693: __ dsrlv(i.OutputRegister(),
i.OutputRegister(), at);
Let's leave the shifts to strip sign extension for now, and re-check later.

[balazs.kilvady, 2015-03-05 18:48:39]

The CQ bit was checked by balazs.kilvady@imgtec.com

[commit-bot: I haz the power, 2015-03-05 18:49:25]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/980073003/40001

[commit-bot: I haz the power, 2015-03-05 19:28:17]

Committed patchset #3 (id:40001)

[commit-bot: I haz the power, 2015-03-05 19:28:41]

Patchset 3 (id:??) landed as
https://crrev.com/b9ed2199bdff292bfdf49fb3d05eb3564ece27bd
Cr-Commit-Position: refs/heads/master@{#27028}