MIPS: [turbofan] Support for %_DoubleHi, %_DoubleLo and %_ConstructDouble.

src/compiler/mips64/instruction-codes-mips64.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 58 matching lines @@
   V(Mips64Lhu)                     \
   V(Mips64Sh)                      \
   V(Mips64Ld)                      \
   V(Mips64Lw)                      \
   V(Mips64Sw)                      \
   V(Mips64Sd)                      \
   V(Mips64Lwc1)                    \
   V(Mips64Swc1)                    \
   V(Mips64Ldc1)                    \
   V(Mips64Sdc1)                    \
+  V(Mips64FmoveLowUwD)             \
+  V(Mips64FmoveLowDUw)             \
+  V(Mips64FmoveHighUwD)            \
+  V(Mips64FmoveHighDUw)            \
   V(Mips64Push)                    \
   V(Mips64StoreToStackSlot)        \
   V(Mips64StackClaim)              \
   V(Mips64StoreWriteBarrier)
 
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
@@ skipping 10 matching lines @@
 #define TARGET_ADDRESSING_MODE_LIST(V) \
   V(MRI) /* [%r0 + K] */               \
   V(MRR) /* [%r0 + %r1] */
 
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_