OLD | NEW |
1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
6 | 6 |
7 #include "src/v8.h" | 7 #include "src/v8.h" |
8 | 8 |
9 #if V8_TARGET_ARCH_MIPS64 | 9 #if V8_TARGET_ARCH_MIPS64 |
10 | 10 |
(...skipping 1699 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1710 } | 1710 } |
1711 } | 1711 } |
1712 } | 1712 } |
1713 | 1713 |
1714 if (bd == PROTECT) { | 1714 if (bd == PROTECT) { |
1715 nop(); | 1715 nop(); |
1716 } | 1716 } |
1717 } | 1717 } |
1718 | 1718 |
1719 | 1719 |
| 1720 void MacroAssembler::FmoveLow(FPURegister dst, Register src_low) { |
| 1721 DCHECK(!src_low.is(at)); |
| 1722 mfhc1(at, dst); |
| 1723 mtc1(src_low, dst); |
| 1724 mthc1(at, dst); |
| 1725 } |
| 1726 |
| 1727 |
1720 void MacroAssembler::Move(FPURegister dst, float imm) { | 1728 void MacroAssembler::Move(FPURegister dst, float imm) { |
1721 li(at, Operand(bit_cast<int32_t>(imm))); | 1729 li(at, Operand(bit_cast<int32_t>(imm))); |
1722 mtc1(at, dst); | 1730 mtc1(at, dst); |
1723 } | 1731 } |
1724 | 1732 |
1725 | 1733 |
1726 void MacroAssembler::Move(FPURegister dst, double imm) { | 1734 void MacroAssembler::Move(FPURegister dst, double imm) { |
1727 static const DoubleRepresentation minus_zero(-0.0); | 1735 static const DoubleRepresentation minus_zero(-0.0); |
1728 static const DoubleRepresentation zero(0.0); | 1736 static const DoubleRepresentation zero(0.0); |
1729 DoubleRepresentation value_rep(imm); | 1737 DoubleRepresentation value_rep(imm); |
(...skipping 4367 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
6097 } | 6105 } |
6098 if (mag.shift > 0) sra(result, result, mag.shift); | 6106 if (mag.shift > 0) sra(result, result, mag.shift); |
6099 srl(at, dividend, 31); | 6107 srl(at, dividend, 31); |
6100 Addu(result, result, Operand(at)); | 6108 Addu(result, result, Operand(at)); |
6101 } | 6109 } |
6102 | 6110 |
6103 | 6111 |
6104 } } // namespace v8::internal | 6112 } } // namespace v8::internal |
6105 | 6113 |
6106 #endif // V8_TARGET_ARCH_MIPS64 | 6114 #endif // V8_TARGET_ARCH_MIPS64 |
OLD | NEW |