Index: src/mips/simulator-mips.cc |
diff --git a/src/mips/simulator-mips.cc b/src/mips/simulator-mips.cc |
index 79f337d3df05a2e18208b97a94977d2330563f93..7ea38419358a600f8c6202f2f30bcdd5c6e350bb 100644 |
--- a/src/mips/simulator-mips.cc |
+++ b/src/mips/simulator-mips.cc |
@@ -1935,7 +1935,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, |
// Logical right-rotate of a word by a fixed number of bits. This |
// is special case of SRL instruction, added in MIPS32 Release 2. |
// RS field is equal to 00001. |
- *alu_out = (rt_u >> sa) | (rt_u << (32 - sa)); |
+ *alu_out = base::bits::RotateRight32(rt_u, sa); |
} |
break; |
case SRA: |
@@ -1953,7 +1953,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, |
// Logical right-rotate of a word by a variable number of bits. |
// This is special case od SRLV instruction, added in MIPS32 |
// Release 2. SA field is equal to 00001. |
- *alu_out = (rt_u >> rs_u) | (rt_u << (32 - rs_u)); |
+ *alu_out = base::bits::RotateRight32(rt_u, rs_u); |
} |
break; |
case SRAV: |