| OLD | NEW |
| 1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include <limits.h> | 5 #include <limits.h> |
| 6 #include <stdarg.h> | 6 #include <stdarg.h> |
| 7 #include <stdlib.h> | 7 #include <stdlib.h> |
| 8 #include <cmath> | 8 #include <cmath> |
| 9 | 9 |
| 10 #include "src/v8.h" | 10 #include "src/v8.h" |
| (...skipping 1917 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1928 break; | 1928 break; |
| 1929 case SRL: | 1929 case SRL: |
| 1930 if (rs_reg == 0) { | 1930 if (rs_reg == 0) { |
| 1931 // Regular logical right shift of a word by a fixed number of | 1931 // Regular logical right shift of a word by a fixed number of |
| 1932 // bits instruction. RS field is always equal to 0. | 1932 // bits instruction. RS field is always equal to 0. |
| 1933 *alu_out = rt_u >> sa; | 1933 *alu_out = rt_u >> sa; |
| 1934 } else { | 1934 } else { |
| 1935 // Logical right-rotate of a word by a fixed number of bits. This | 1935 // Logical right-rotate of a word by a fixed number of bits. This |
| 1936 // is special case of SRL instruction, added in MIPS32 Release 2. | 1936 // is special case of SRL instruction, added in MIPS32 Release 2. |
| 1937 // RS field is equal to 00001. | 1937 // RS field is equal to 00001. |
| 1938 *alu_out = (rt_u >> sa) | (rt_u << (32 - sa)); | 1938 *alu_out = base::bits::RotateRight32(rt_u, sa); |
| 1939 } | 1939 } |
| 1940 break; | 1940 break; |
| 1941 case SRA: | 1941 case SRA: |
| 1942 *alu_out = rt >> sa; | 1942 *alu_out = rt >> sa; |
| 1943 break; | 1943 break; |
| 1944 case SLLV: | 1944 case SLLV: |
| 1945 *alu_out = rt << rs; | 1945 *alu_out = rt << rs; |
| 1946 break; | 1946 break; |
| 1947 case SRLV: | 1947 case SRLV: |
| 1948 if (sa == 0) { | 1948 if (sa == 0) { |
| 1949 // Regular logical right-shift of a word by a variable number of | 1949 // Regular logical right-shift of a word by a variable number of |
| 1950 // bits instruction. SA field is always equal to 0. | 1950 // bits instruction. SA field is always equal to 0. |
| 1951 *alu_out = rt_u >> rs; | 1951 *alu_out = rt_u >> rs; |
| 1952 } else { | 1952 } else { |
| 1953 // Logical right-rotate of a word by a variable number of bits. | 1953 // Logical right-rotate of a word by a variable number of bits. |
| 1954 // This is special case od SRLV instruction, added in MIPS32 | 1954 // This is special case od SRLV instruction, added in MIPS32 |
| 1955 // Release 2. SA field is equal to 00001. | 1955 // Release 2. SA field is equal to 00001. |
| 1956 *alu_out = (rt_u >> rs_u) | (rt_u << (32 - rs_u)); | 1956 *alu_out = base::bits::RotateRight32(rt_u, rs_u); |
| 1957 } | 1957 } |
| 1958 break; | 1958 break; |
| 1959 case SRAV: | 1959 case SRAV: |
| 1960 *alu_out = rt >> rs; | 1960 *alu_out = rt >> rs; |
| 1961 break; | 1961 break; |
| 1962 case MFHI: // MFHI == CLZ on R6. | 1962 case MFHI: // MFHI == CLZ on R6. |
| 1963 if (!IsMipsArchVariant(kMips32r6)) { | 1963 if (!IsMipsArchVariant(kMips32r6)) { |
| 1964 DCHECK(instr->SaValue() == 0); | 1964 DCHECK(instr->SaValue() == 0); |
| 1965 *alu_out = get_register(HI); | 1965 *alu_out = get_register(HI); |
| 1966 } else { | 1966 } else { |
| (...skipping 1293 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 3260 } | 3260 } |
| 3261 | 3261 |
| 3262 | 3262 |
| 3263 #undef UNSUPPORTED | 3263 #undef UNSUPPORTED |
| 3264 | 3264 |
| 3265 } } // namespace v8::internal | 3265 } } // namespace v8::internal |
| 3266 | 3266 |
| 3267 #endif // USE_SIMULATOR | 3267 #endif // USE_SIMULATOR |
| 3268 | 3268 |
| 3269 #endif // V8_TARGET_ARCH_MIPS | 3269 #endif // V8_TARGET_ARCH_MIPS |
| OLD | NEW |