| Index: src/mips64/simulator-mips64.cc
|
| diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
|
| index bb39b97cca82003e9d46adae5f2381b192e0ecf6..95b9fce7fc34a055abf95da695b024a8613847d7 100644
|
| --- a/src/mips64/simulator-mips64.cc
|
| +++ b/src/mips64/simulator-mips64.cc
|
| @@ -2012,7 +2012,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
|
| // Logical right-rotate of a word by a fixed number of bits. This
|
| // is special case of SRL instruction, added in MIPS32 Release 2.
|
| // RS field is equal to 00001.
|
| - *alu_out = ((uint32_t)rt_u >> sa) | ((uint32_t)rt_u << (32 - sa));
|
| + *alu_out = base::bits::RotateRight32((uint32_t)rt_u, sa);
|
| }
|
| break;
|
| case DSRL:
|
| @@ -2045,8 +2045,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
|
| // Logical right-rotate of a word by a variable number of bits.
|
| // This is special case od SRLV instruction, added in MIPS32
|
| // Release 2. SA field is equal to 00001.
|
| - *alu_out =
|
| - ((uint32_t)rt_u >> rs_u) | ((uint32_t)rt_u << (32 - rs_u));
|
| + *alu_out = base::bits::RotateRight32(((uint32_t)rt_u, rs_u);
|
| }
|
| break;
|
| case DSRLV:
|
| @@ -2058,7 +2057,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
|
| // Logical right-rotate of a word by a variable number of bits.
|
| // This is special case od SRLV instruction, added in MIPS32
|
| // Release 2. SA field is equal to 00001.
|
| - *alu_out = (rt_u >> rs_u) | (rt_u << (32 - rs_u));
|
| + *alu_out = base::bits::RotateRight32(rt_u, rs_u);
|
| }
|
| break;
|
| case SRAV:
|
|
|