Subzero: Use the linear-scan register allocator for Om1 as well.

Subzero: Use the linear-scan register allocator for Om1 as well.

This removes the need for Om1's postLower() code which did its own ad-hoc register allocation.  And it actually speeds up Om1 translation significantly.

This mode of register allocation only allocates for infinite-weight Variables, while respecting live ranges of pre-colored Variables.

BUG= none
R=jvoung@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=70d0a054b3a2ed6ee49b2bf5d94cf52d79bbb1b9

[Jim Stichnoth, 2014-11-14 22:11:58]

stichnot@chromium.org changed reviewers:
+ jvoung@chromium.org

[Jim Stichnoth, 2014-11-14 22:14:34]

https://codereview.chromium.org/733643005/diff/1/src/IceTranslator.cpp
File src/IceTranslator.cpp (left):

https://codereview.chromium.org/733643005/diff/1/src/IceTranslator.cpp#oldcode86
src/IceTranslator.cpp:86: if (Ctx->getFlags().UseIntegratedAssembler) {
Without the !ErrorStatus guard, Om1 was aborting during emission when
encountering an infinite-weight Variable without a register, and the "wrong"
error was causing one of the lit tests to fail.

[jvoung (off chromium), 2014-11-14 23:26:22]

Cool -- just some small nits, otherwise LGTM

https://codereview.chromium.org/733643005/diff/20001/src/IceRegAlloc.cpp
File src/IceRegAlloc.cpp (right):

https://codereview.chromium.org/733643005/diff/20001/src/IceRegAlloc.cpp#newc...
src/IceRegAlloc.cpp:200: // This isn't actually a fatal considition, but it
would be nice to
"considition -> condition"

https://codereview.chromium.org/733643005/diff/20001/src/IceRegAlloc.cpp#newc...
src/IceRegAlloc.cpp:205: // infinite-weight Variable has a live range spanning a
call.
It might be nice to have a assert-level verifier pass at some point if this
becomes a problem, but yeah I don't see when that would happen w/ this.

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLowering.h
File src/IceTargetLowering.h (right):

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLowering.h#...
src/IceTargetLowering.h:241: // allocate registers based on affinity and other
factors.  The
Update the postLower comment?

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
File src/IceTargetLoweringX8632.cpp (left):

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
src/IceTargetLoweringX8632.cpp:13: // TargetX8632Fast::postLower() which does
the simplest possible
This comment about what postLower() does can be updated now.

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
src/IceTargetLoweringX8632.cpp:1819: // TODO: Consider calling postLower() here
to reduce the register
This postLower comment may not apply anymore?

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
File src/IceTargetLoweringX8632.cpp (right):

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
src/IceTargetLoweringX8632.cpp:4120: // TODO(stichnot): Use postLower() in -Om1
mode to avoid buildup of
similar?

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
src/IceTargetLoweringX8632.cpp:4208: // Register set setup similar to regAlloc()
and postLower().
similar comment about postLower

[Jim Stichnoth, 2014-11-14 23:51:35]

https://codereview.chromium.org/733643005/diff/20001/src/IceRegAlloc.cpp
File src/IceRegAlloc.cpp (right):

https://codereview.chromium.org/733643005/diff/20001/src/IceRegAlloc.cpp#newc...
src/IceRegAlloc.cpp:200: // This isn't actually a fatal considition, but it
would be nice to
On 2014/11/14 23:26:22, jvoung wrote:
> "considition -> condition"

Done.

https://codereview.chromium.org/733643005/diff/20001/src/IceRegAlloc.cpp#newc...
src/IceRegAlloc.cpp:205: // infinite-weight Variable has a live range spanning a
call.
On 2014/11/14 23:26:22, jvoung wrote:
> It might be nice to have a assert-level verifier pass at some point if this
> becomes a problem, but yeah I don't see when that would happen w/ this.

Agreed.  Also to verify things like monotonically increasing instruction
numbers.

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLowering.h
File src/IceTargetLowering.h (right):

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLowering.h#...
src/IceTargetLowering.h:241: // allocate registers based on affinity and other
factors.  The
On 2014/11/14 23:26:22, jvoung wrote:
> Update the postLower comment?

Ewww.  That comment I think was a relic of the early idea of "multi-block
register allocation" which I abandoned.

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
File src/IceTargetLoweringX8632.cpp (left):

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
src/IceTargetLoweringX8632.cpp:13: // TargetX8632Fast::postLower() which does
the simplest possible
On 2014/11/14 23:26:22, jvoung wrote:
> This comment about what postLower() does can be updated now.

Done.

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
src/IceTargetLoweringX8632.cpp:1819: // TODO: Consider calling postLower() here
to reduce the register
On 2014/11/14 23:26:22, jvoung wrote:
> This postLower comment may not apply anymore?

Done.

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
File src/IceTargetLoweringX8632.cpp (right):

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
src/IceTargetLoweringX8632.cpp:4120: // TODO(stichnot): Use postLower() in -Om1
mode to avoid buildup of
On 2014/11/14 23:26:22, jvoung wrote:
> similar?

Done.

https://codereview.chromium.org/733643005/diff/20001/src/IceTargetLoweringX86...
src/IceTargetLoweringX8632.cpp:4208: // Register set setup similar to regAlloc()
and postLower().
On 2014/11/14 23:26:22, jvoung wrote:
> similar comment about postLower 

Done.

[Jim Stichnoth, 2014-11-14 23:53:49]

Committed patchset #3 (id:40001) manually as
70d0a054b3a2ed6ee49b2bf5d94cf52d79bbb1b9 (presubmit successful).