Handle add, adc, etc., mfence, div, idiv, mul in the assembler.

Handle add, adc, etc., mfence, div, idiv, mul in the assembler.

Add a test to check that the encodings are efficient for immediates
(chooses the i8, and eax encodings when appropriate).

The .byte syntax breaks NaCl bundle straddle checking in llvm-mc,
so I had to change one of the tests which noted that a nop appeared
(no longer does).

This also assumes that _add(), etc. are usually done with _add(T, ...) and
then _mov(dst, T) so that the dest is always register.

BUG=none
R=stichnot@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=af2780c287ec6573d433c6d119f558c98eae05e1

[jvoung (off chromium), 2014-09-25 20:05:16]

jvoung@chromium.org changed reviewers:
+ stichnot@chromium.org

[jvoung (off chromium), 2014-09-25 20:05:53]

https://codereview.chromium.org/604873003/diff/1/src/assembler_ia32.cpp
File src/assembler_ia32.cpp (right):

https://codereview.chromium.org/604873003/diff/1/src/assembler_ia32.cpp#newco...
src/assembler_ia32.cpp:1202: if (Ty == IceType_i8 || Ty == IceType_i1)
Turns out that most of the i8 || i1 are in this file. The ones in targetlowering
are mostly i8 since arith instructions only allow i8, and only the bitwise ops
allow i1.

I think in the next CL I'll refactor this -- have a function for i8 which could
assert if it sees i1, and have a function that allows both?

[Jim Stichnoth, 2014-09-26 02:31:37]

lgtm

https://codereview.chromium.org/604873003/diff/1/src/IceInstX8632.cpp
File src/IceInstX8632.cpp (right):

https://codereview.chromium.org/604873003/diff/1/src/IceInstX8632.cpp#newcode350
src/IceInstX8632.cpp:350: Str.write_hex(Asm->LoadBuffer<uint8_t>(StartPosition +
i));
Thanks! :)

https://codereview.chromium.org/604873003/diff/1/src/assembler_ia32.cpp
File src/assembler_ia32.cpp (right):

https://codereview.chromium.org/604873003/diff/1/src/assembler_ia32.cpp#newco...
src/assembler_ia32.cpp:1202: if (Ty == IceType_i8 || Ty == IceType_i1)
On 2014/09/25 20:05:53, jvoung wrote:
> Turns out that most of the i8 || i1 are in this file. The ones in
targetlowering
> are mostly i8 since arith instructions only allow i8, and only the bitwise ops
> allow i1.
> 
> I think in the next CL I'll refactor this -- have a function for i8 which
could
> assert if it sees i1, and have a function that allows both?

That sounds good.  There are also a couple other pattern to refactor: checking
for floating point scalars, and checking for 64-bit scalars.  Maybe more?

https://codereview.chromium.org/604873003/diff/1/tests_lit/assembler/x86/imme...
File tests_lit/assembler/x86/immediate_encodings.ll (right):

https://codereview.chromium.org/604873003/diff/1/tests_lit/assembler/x86/imme...
tests_lit/assembler/x86/immediate_encodings.ll:45: ; CHECK: 80 f1 7f xor
{{[^a]}}l, 127
(This applies to testXor32Imm32NotEAX as well.)

You listed the entire 3-byte encoding, which would seem to fix a particular
register?  I would say either list one of the registers explicitly, or use
another regex for the encoding that captures the 3 (?) possibilities.

[jvoung (off chromium), 2014-09-26 16:25:50]

https://codereview.chromium.org/604873003/diff/1/tests_lit/assembler/x86/imme...
File tests_lit/assembler/x86/immediate_encodings.ll (right):

https://codereview.chromium.org/604873003/diff/1/tests_lit/assembler/x86/imme...
tests_lit/assembler/x86/immediate_encodings.ll:45: ; CHECK: 80 f1 7f xor
{{[^a]}}l, 127
On 2014/09/26 02:31:36, stichnot wrote:
> (This applies to testXor32Imm32NotEAX as well.)
> 
> You listed the entire 3-byte encoding, which would seem to fix a particular
> register?  I would say either list one of the registers explicitly, or use
> another regex for the encoding that captures the 3 (?) possibilities.

Ah good point =)

Added regex of 1-3, for c, d, and b.

[jvoung (off chromium), 2014-09-26 18:14:35]

Committed patchset #3 (id:40001) manually as af2780c (presubmit successful).