Handle a few more instructions in assembler (cmov, cdq, cmpxchg, xadd, xchg).

src/assembler_ia32.cpp

Index: src/assembler_ia32.cpp
diff --git a/src/assembler_ia32.cpp b/src/assembler_ia32.cpp
index ceed1d109c8920031905a7101ba1f120468598c5..5d1c8a71280afcbf1ce2c02fde22ddcfad1959d3 100644
--- a/src/assembler_ia32.cpp
+++ b/src/assembler_ia32.cpp
@@ -1110,12 +1110,6 @@ void AssemblerX86::fincstp() {
   EmitUint8(0xF7);
 }
 
-void AssemblerX86::xchgl(GPRRegister dst, GPRRegister src) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(0x87);
-  EmitRegisterOperand(dst, src);
-}
-
 void AssemblerX86::cmpl(GPRRegister reg, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(7, Operand(reg), imm);
@@ -1307,6 +1301,18 @@ void AssemblerX86::subl(const Address &address, GPRRegister reg) {
   EmitOperand(reg, address);
 }
 
+void AssemblerX86::cbw() {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandSizeOverride();
+  EmitUint8(0x98);
+}
+
+void AssemblerX86::cwd() {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandSizeOverride();
+  EmitUint8(0x99);
+}
+
 void AssemblerX86::cdq() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x99);
@@ -1674,13 +1680,48 @@ void AssemblerX86::lock() {
   EmitUint8(0xF0);
 }
 
-void AssemblerX86::cmpxchgl(const Address &address, GPRRegister reg) {
+void AssemblerX86::cmpxchg(Type Ty, const Address &address, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
   EmitUint8(0x0F);
-  EmitUint8(0xB1);
+  if (Ty == IceType_i1 || Ty == IceType_i8)

[Jim Stichnoth, 2014/09/23 17:21:20]

After the dust settles, I think there are a lot of type checks like that that
should be factored out into helper functions.  Most of this is in
IceTargetLoweringX8632.cpp.

[jvoung (off chromium), 2014/09/23 20:20:56]

Acknowledged.


Yep -- Agreed. Technically there shouldn't be a cmpxchg w/ i1, since we don't
support atomics on i1 so I could remove that. Otherwise some of the other ops
will see i1 and need to use the byte form.

+    EmitUint8(0xB0);
+  else
+    EmitUint8(0xB1);
   EmitOperand(reg, address);
 }
 
+void AssemblerX86::cmpxchg8b(const Address &address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitUint8(0x0F);
+  EmitUint8(0xC7);
+  EmitOperand(1, address);
+}
+
+void AssemblerX86::xadd(Type Ty, const Address &addr, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
+  EmitUint8(0x0F);
+  if (Ty == IceType_i1 || Ty == IceType_i8)
+    EmitUint8(0xC0);
+  else
+    EmitUint8(0xC1);
+  EmitOperand(reg, addr);
+}
+
+void AssemblerX86::xchg(Type Ty, const Address &addr, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
+  if (Ty == IceType_i1 || Ty == IceType_i8)
+    EmitUint8(0x86);
+  else
+    EmitUint8(0x87);
+  EmitOperand(reg, addr);
+}
+
 void AssemblerX86::Align(intptr_t alignment, intptr_t offset) {
   assert(llvm::isPowerOf2_32(alignment));
   intptr_t pos = offset + buffer_.GetPosition();