Handle a few more instructions in assembler (cmov, cdq, cmpxchg, xadd, xchg).

src/assembler_ia32.cpp

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===- subzero/src/assembler_ia32.cpp - Assembler for x86-32  -------------===//
 //
 //                        The Subzero Code Generator
 //
@@ skipping 1092 matching lines @@
   EmitUint8(0xDB);
   EmitOperand(0, src);
 }
 
 void AssemblerX86::fincstp() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitUint8(0xF7);
 }
 
-void AssemblerX86::xchgl(GPRRegister dst, GPRRegister src) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(0x87);
-  EmitRegisterOperand(dst, src);
-}
-
 void AssemblerX86::cmpl(GPRRegister reg, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(7, Operand(reg), imm);
 }
 
 void AssemblerX86::cmpl(GPRRegister reg0, GPRRegister reg1) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x3B);
   EmitOperand(reg0, Operand(reg1));
 }
@@ skipping 171 matching lines @@
   EmitUint8(0x2B);
   EmitOperand(reg, address);
 }
 
 void AssemblerX86::subl(const Address &address, GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x29);
   EmitOperand(reg, address);
 }
 
+void AssemblerX86::cbw() {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandSizeOverride();
+  EmitUint8(0x98);
+}
+
+void AssemblerX86::cwd() {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandSizeOverride();
+  EmitUint8(0x99);
+}
+
 void AssemblerX86::cdq() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x99);
 }
 
 void AssemblerX86::idivl(GPRRegister reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitUint8(0xF8 | reg);
 }
@@ skipping 347 matching lines @@
   EmitUint8(0xE9);
   EmitFixup(DirectCallRelocation::create(this, FK_PcRel_4, label));
   EmitInt32(-4);
 }
 
 void AssemblerX86::lock() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF0);
 }
 
-void AssemblerX86::cmpxchgl(const Address &address, GPRRegister reg) {
+void AssemblerX86::cmpxchg(Type Ty, const Address &address, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
+  EmitUint8(0x0F);
+  if (Ty == IceType_i1 || Ty == IceType_i8)

[Jim Stichnoth, 2014/09/23 17:21:20]

After the dust settles, I think there are a lot of type checks like that that
should be factored out into helper functions.  Most of this is in
IceTargetLoweringX8632.cpp.

[jvoung (off chromium), 2014/09/23 20:20:56]

Acknowledged.


Yep -- Agreed. Technically there shouldn't be a cmpxchg w/ i1, since we don't
support atomics on i1 so I could remove that. Otherwise some of the other ops
will see i1 and need to use the byte form.

+    EmitUint8(0xB0);
+  else
+    EmitUint8(0xB1);
+  EmitOperand(reg, address);
+}
+
+void AssemblerX86::cmpxchg8b(const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
-  EmitUint8(0xB1);
-  EmitOperand(reg, address);
+  EmitUint8(0xC7);
+  EmitOperand(1, address);
+}
+
+void AssemblerX86::xadd(Type Ty, const Address &addr, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
+  EmitUint8(0x0F);
+  if (Ty == IceType_i1 || Ty == IceType_i8)
+    EmitUint8(0xC0);
+  else
+    EmitUint8(0xC1);
+  EmitOperand(reg, addr);
+}
+
+void AssemblerX86::xchg(Type Ty, const Address &addr, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
+  if (Ty == IceType_i1 || Ty == IceType_i8)
+    EmitUint8(0x86);
+  else
+    EmitUint8(0x87);
+  EmitOperand(reg, addr);
 }
 
 void AssemblerX86::Align(intptr_t alignment, intptr_t offset) {
   assert(llvm::isPowerOf2_32(alignment));
   intptr_t pos = offset + buffer_.GetPosition();
   intptr_t mod = pos & (alignment - 1);
   if (mod == 0) {
     return;
   }
   intptr_t bytes_needed = alignment - mod;
@@ skipping 121 matching lines @@
 void AssemblerX86::EmitGenericShift(int rm, const Operand &operand,
                                     GPRRegister shifter) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   assert(shifter == RegX8632::Encoded_Reg_ecx);
   EmitUint8(0xD3);
   EmitOperand(rm, Operand(operand));
 }
 
 } // end of namespace x86
 } // end of namespace Ice