Unify MachineType and RepType.

src/compiler/arm/instruction-selector-arm.cc

Index: src/compiler/arm/instruction-selector-arm.cc
diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
index 029d6e3b96e9d0c61ca3d9e03301afbfe6ffae56..d17f7579f7246094bbab59932616a7776a071bd6 100644
--- a/src/compiler/arm/instruction-selector-arm.cc
+++ b/src/compiler/arm/instruction-selector-arm.cc
@@ -305,28 +305,29 @@ static void VisitBinop(InstructionSelector* selector, Node* node,
 
 
 void InstructionSelector::VisitLoad(Node* node) {
-  MachineType rep = OpParameter<MachineType>(node);
+  MachineType rep = RepresentationOf(OpParameter<MachineType>(node));
   ArmOperandGenerator g(this);
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
 
-  InstructionOperand* result = rep == kMachineFloat64
-                                   ? g.DefineAsDoubleRegister(node)
-                                   : g.DefineAsRegister(node);
+  InstructionOperand* result = rep == rFloat64 ? g.DefineAsDoubleRegister(node)
+                                               : g.DefineAsRegister(node);
 
   ArchOpcode opcode;
+  // TODO(titzer): signed/unsigned small loads
   switch (rep) {
-    case kMachineFloat64:
+    case rFloat64:
       opcode = kArmFloat64Load;
       break;
-    case kMachineWord8:
+    case rBit:  // Fall through.
+    case rWord8:
       opcode = kArmLoadWord8;
       break;
-    case kMachineWord16:
+    case rWord16:
       opcode = kArmLoadWord16;
       break;
-    case kMachineTagged:  // Fall through.
-    case kMachineWord32:
+    case rTagged:  // Fall through.
+    case rWord32:
       opcode = kArmLoadWord32;
       break;
     default:
@@ -354,9 +355,9 @@ void InstructionSelector::VisitStore(Node* node) {
   Node* value = node->InputAt(2);
 
   StoreRepresentation store_rep = OpParameter<StoreRepresentation>(node);
-  MachineType rep = store_rep.rep;
+  MachineType rep = RepresentationOf(store_rep.machine_type);
   if (store_rep.write_barrier_kind == kFullWriteBarrier) {
-    DCHECK(rep == kMachineTagged);
+    DCHECK(rep == rTagged);
     // TODO(dcarney): refactor RecordWrite function to take temp registers
     //                and pass them here instead of using fixed regs
     // TODO(dcarney): handle immediate indices.
@@ -367,22 +368,23 @@ void InstructionSelector::VisitStore(Node* node) {
     return;
   }
   DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
-  InstructionOperand* val = rep == kMachineFloat64 ? g.UseDoubleRegister(value)
-                                                   : g.UseRegister(value);
+  InstructionOperand* val =
+      rep == rFloat64 ? g.UseDoubleRegister(value) : g.UseRegister(value);
 
   ArchOpcode opcode;
   switch (rep) {
-    case kMachineFloat64:
+    case rFloat64:
       opcode = kArmFloat64Store;
       break;
-    case kMachineWord8:
+    case rBit:  // Fall through.
+    case rWord8:
       opcode = kArmStoreWord8;
       break;
-    case kMachineWord16:
+    case rWord16:
       opcode = kArmStoreWord16;
       break;
-    case kMachineTagged:  // Fall through.
-    case kMachineWord32:
+    case rTagged:  // Fall through.
+    case rWord32:
       opcode = kArmStoreWord32;
       break;
     default: