MIPS: Enable aligned keyed stores and loads for double arrays.

MIPS: Enable aligned keyed stores and loads for double arrays.

Provide ~20% performance improvement in Navier-Stokes benchmark, by using
true load/store double (ldc1/sdc1) instructions.

These instructions require double-aligned memory address.
Since doubles are not generally aligned in v8, we historically have used
a workaround using a pair of 32-bit loads/stores (lwc1/swc1), which is slow.

This CL requires FixedDoubleArrays to be aligned in all cases, which is achieved
via these related CL's: https://chromiumcodereview.appspot.com/35103002,
https://chromiumcodereview.appspot.com/35133002,
https://chromiumcodereview.appspot.com/35313002.

TEST=
BUG=

[dusmil, 2013-10-22 16:41:15]

PTAL