MIPS: Enable aligned keyed stores and loads for double arrays.

src/mips/assembler-mips.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1612 matching lines @@
 
 
 //--------Coprocessor-instructions----------------
 
 // Load, store, move.
 void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
   GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
 }
 
 
-void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
+void Assembler::ldc1(FPURegister fd, const MemOperand& src, bool aligned) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // load to two 32-bit loads.
-  GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
-  FPURegister nextfpreg;
-  nextfpreg.setcode(fd.code() + 1);
-  GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ + 4);
+  if (aligned) {
+    GenInstrImmediate(LDC1, src.rm(), fd, src.offset_);
+  } else {
+    GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
+    FPURegister nextfpreg;
+    nextfpreg.setcode(fd.code() + 1);
+    GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ + 4);
+  }
 }
 
 
 void Assembler::swc1(FPURegister fd, const MemOperand& src) {
   GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
 }
 
 
-void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
+void Assembler::sdc1(FPURegister fd, const MemOperand& src, bool aligned) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // store to two 32-bit stores.
-  GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
-  FPURegister nextfpreg;
-  nextfpreg.setcode(fd.code() + 1);
-  GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ + 4);
+  if (aligned) {
+    GenInstrImmediate(SDC1, src.rm(), fd, src.offset_);
+  } else {
+    GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
+    FPURegister nextfpreg;
+    nextfpreg.setcode(fd.code() + 1);
+    GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ + 4);
+  }
 }
 
 
 void Assembler::mtc1(Register rt, FPURegister fs) {
   GenInstrRegister(COP1, MTC1, rt, fs, f0);
 }
 
 
 void Assembler::mfc1(Register rt, FPURegister fs) {
   GenInstrRegister(COP1, MFC1, rt, fs, f0);
@@ skipping 628 matching lines @@
   }
 
   if (patched) {
       CPU::FlushICache(pc+2, sizeof(Address));
   }
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS