MIPS: Enable aligned keyed stores and loads for double arrays.

src/mips/assembler-mips.cc

Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index 0972a8295cbe40ab049649d9035c783f3cf42e8d..362bf9eca0186284dbf8a187671fca1d3c4a3e2a 100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -1630,13 +1630,17 @@ void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
 }
 
 
-void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
+void Assembler::ldc1(FPURegister fd, const MemOperand& src, bool aligned) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // load to two 32-bit loads.
-  GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
-  FPURegister nextfpreg;
-  nextfpreg.setcode(fd.code() + 1);
-  GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ + 4);
+  if (aligned) {
+    GenInstrImmediate(LDC1, src.rm(), fd, src.offset_);
+  } else {
+    GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
+    FPURegister nextfpreg;
+    nextfpreg.setcode(fd.code() + 1);
+    GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ + 4);
+  }
 }
 
 
@@ -1645,13 +1649,17 @@ void Assembler::swc1(FPURegister fd, const MemOperand& src) {
 }
 
 
-void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
+void Assembler::sdc1(FPURegister fd, const MemOperand& src, bool aligned) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // store to two 32-bit stores.
-  GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
-  FPURegister nextfpreg;
-  nextfpreg.setcode(fd.code() + 1);
-  GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ + 4);
+  if (aligned) {
+    GenInstrImmediate(SDC1, src.rm(), fd, src.offset_);
+  } else {
+    GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
+    FPURegister nextfpreg;
+    nextfpreg.setcode(fd.code() + 1);
+    GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ + 4);
+  }
 }