[ARM] Improve VFP register moves.

test/cctest/test-disasm-arm.cc

Index: test/cctest/test-disasm-arm.cc
diff --git a/test/cctest/test-disasm-arm.cc b/test/cctest/test-disasm-arm.cc
index 4a80e702304a479edefad714bac13714babfbc79..89f8819a252eb385de5eafdbf4f16ec8f21d7395 100644
--- a/test/cctest/test-disasm-arm.cc
+++ b/test/cctest/test-disasm-arm.cc
@@ -994,10 +994,14 @@ TEST(Neon) {
               "eea24b30       vdup.16 q1, r4");
       COMPARE(vdup(Neon32, q15, r1),
               "eeae1b90       vdup.32 q15, r1");
-      COMPARE(vdup(q0, s3),
-              "f3bc0c41       vdup q0, d1[1]");
-      COMPARE(vdup(q15, s2),
-              "f3f4ec41       vdup q15, d1[0]");
+      COMPARE(vdup(Neon32, q0, d1, 1),
+              "f3bc0c41       vdup.32 q0, d1[1]");
+      COMPARE(vdup(Neon32, q15, d1, 0),
+              "f3f4ec41       vdup.32 q15, d1[0]");
+      COMPARE(vdup(Neon16, q7, d8, 3),
+              "f3beec48       vdup.16 q7, d8[3]");
+      COMPARE(vdup(Neon32, d0, d30, 0),
+              "f3b40c2e       vdup.32 d0, d30[0]");
       COMPARE(vcvt_f32_s32(q15, q1),
               "f3fbe642       vcvt.f32.s32 q15, q1");
       COMPARE(vcvt_f32_u32(q8, q9),
@@ -1106,6 +1110,14 @@ TEST(Neon) {
               "f3d6e050       vshr.u16 q15, q0, #10");
       COMPARE(vshr(NeonS32, q15, q0, 17),
               "f2efe050       vshr.s32 q15, q0, #17");
+      COMPARE(vsli(Neon64, d2, d0, 32),
+              "f3a02590       vsli.64 d2, d0, #32");
+      COMPARE(vsli(Neon32, d7, d8, 17),
+              "f3b17518       vsli.32 d7, d8, #17");
+      COMPARE(vsri(Neon64, d2, d0, 32),
+              "f3a02490       vsri.64 d2, d0, #32");
+      COMPARE(vsri(Neon16, d7, d8, 8),
+              "f3987418       vsri.16 d7, d8, #8");
       COMPARE(vrecpe(q15, q0),
               "f3fbe540       vrecpe.f32 q15, q0");
       COMPARE(vrecps(q15, q0, q8),