[ARM] Improve VFP register moves.

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 976 matching lines @@
       COMPARE(vswp(q0, q15),
               "f3b2006e       vswp q0, q15");
       COMPARE(vswp(q8, q9),
               "f3f20062       vswp q8, q9");
       COMPARE(vdup(Neon8, q0, r0),
               "eee00b10       vdup.8 q0, r0");
       COMPARE(vdup(Neon16, q1, r4),
               "eea24b30       vdup.16 q1, r4");
       COMPARE(vdup(Neon32, q15, r1),
               "eeae1b90       vdup.32 q15, r1");
-      COMPARE(vdup(q0, s3),
-              "f3bc0c41       vdup q0, d1[1]");
-      COMPARE(vdup(q15, s2),
-              "f3f4ec41       vdup q15, d1[0]");
+      COMPARE(vdup(Neon32, q0, d1, 1),
+              "f3bc0c41       vdup.32 q0, d1[1]");
+      COMPARE(vdup(Neon32, q15, d1, 0),
+              "f3f4ec41       vdup.32 q15, d1[0]");
+      COMPARE(vdup(Neon16, q7, d8, 3),
+              "f3beec48       vdup.16 q7, d8[3]");
+      COMPARE(vdup(Neon32, d0, d30, 0),
+              "f3b40c2e       vdup.32 d0, d30[0]");
       COMPARE(vcvt_f32_s32(q15, q1),
               "f3fbe642       vcvt.f32.s32 q15, q1");
       COMPARE(vcvt_f32_u32(q8, q9),
               "f3fb06e2       vcvt.f32.u32 q8, q9");
       COMPARE(vcvt_s32_f32(q15, q1),
               "f3fbe742       vcvt.s32.f32 q15, q1");
       COMPARE(vcvt_u32_f32(q8, q9),
               "f3fb07e2       vcvt.u32.f32 q8, q9");
       COMPARE(vabs(q0, q1),
               "f3b90742       vabs.f32 q0, q1");
@@ skipping 88 matching lines @@
       COMPARE(vshl(NeonU16, q15, q0, 10),
               "f2dae550       vshl.i16 q15, q0, #10");
       COMPARE(vshl(NeonS32, q15, q0, 17),
               "f2f1e550       vshl.i32 q15, q0, #17");
       COMPARE(vshr(NeonS8, q15, q0, 6),
               "f2cae050       vshr.s8 q15, q0, #6");
       COMPARE(vshr(NeonU16, q15, q0, 10),
               "f3d6e050       vshr.u16 q15, q0, #10");
       COMPARE(vshr(NeonS32, q15, q0, 17),
               "f2efe050       vshr.s32 q15, q0, #17");
+      COMPARE(vsli(Neon64, d2, d0, 32),
+              "f3a02590       vsli.64 d2, d0, #32");
+      COMPARE(vsli(Neon32, d7, d8, 17),
+              "f3b17518       vsli.32 d7, d8, #17");
+      COMPARE(vsri(Neon64, d2, d0, 32),
+              "f3a02490       vsri.64 d2, d0, #32");
+      COMPARE(vsri(Neon16, d7, d8, 8),
+              "f3987418       vsri.16 d7, d8, #8");
       COMPARE(vrecpe(q15, q0),
               "f3fbe540       vrecpe.f32 q15, q0");
       COMPARE(vrecps(q15, q0, q8),
               "f240ef70       vrecps.f32 q15, q0, q8");
       COMPARE(vrsqrte(q15, q0),
               "f3fbe5c0       vrsqrte.f32 q15, q0");
       COMPARE(vrsqrts(q15, q0, q8),
               "f260ef70       vrsqrts.f32 q15, q0, q8");
       COMPARE(vtst(Neon8, q0, q1, q2),
               "f2020854       vtst.i8 q0, q1, q2");
@@ skipping 377 matching lines @@
 
   COMPARE(ldrexb(r0, r1), "e1d10f9f       ldrexb r0, [r1]");
   COMPARE(strexb(r0, r1, r2), "e1c20f91       strexb r0, r1, [r2]");
   COMPARE(ldrexh(r0, r1), "e1f10f9f       ldrexh r0, [r1]");
   COMPARE(strexh(r0, r1, r2), "e1e20f91       strexh r0, r1, [r2]");
   COMPARE(ldrex(r0, r1), "e1910f9f       ldrex r0, [r1]");
   COMPARE(strex(r0, r1, r2), "e1820f91       strex r0, r1, [r2]");
 
   VERIFY_RUN();
 }