Adds intrinsics for arm64.

runtime/vm/assembler_arm64.h

Index: runtime/vm/assembler_arm64.h
===================================================================
--- runtime/vm/assembler_arm64.h	(revision 36300)
+++ runtime/vm/assembler_arm64.h	(working copy)
@@ -473,6 +473,9 @@
   void and_(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(AND, rd, rn, o, kDoubleWord);
   }
+  void andw_(Register rd, Register rn, Operand o) {
+    EmitLogicalShiftOp(AND, rd, rn, o, kWord);
+  }
   void bic(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(BIC, rd, rn, o, kDoubleWord);
   }
@@ -485,6 +488,9 @@
   void eor(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(EOR, rd, rn, o, kDoubleWord);
   }
+  void eorw(Register rd, Register rn, Operand o) {
+    EmitLogicalShiftOp(EOR, rd, rn, o, kWord);
+  }
   void eon(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(EON, rd, rn, o, kDoubleWord);
   }
@@ -780,9 +786,15 @@
   void Lsl(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, LSL, shift));
   }
+  void Lslw(Register rd, Register rn, int shift) {
+    addw(rd, ZR, Operand(rn, LSL, shift));
+  }
   void Lsr(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, LSR, shift));
   }
+  void Lsrw(Register rd, Register rn, int shift) {
+    addw(rd, ZR, Operand(rn, LSR, shift));

[regis, 2014/05/19 20:14:02]

Is a shift amount > 31 allowed? Are all 64 bits of rn taken into consideration?

[zra, 2014/05/19 21:13:18]

Ah, no. A shift > 31 is not allowed. I've added an ASSERT. Instructions in
32-bit mode only operate on the bottom 32 bits, so this instruction will shift
in zeros.

+  }
   void Asr(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, ASR, shift));
   }