Adds intrinsics for arm64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 455 matching lines @@
     Operand imm_op;
     const bool immok = Operand::IsImmLogical(imm, kXRegSizeInBits, &imm_op);
     ASSERT(immok);
     EmitLogicalImmOp(ANDIS, rd, rn, imm_op, kDoubleWord);
   }
 
   // Logical (shifted) register operations.
   void and_(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(AND, rd, rn, o, kDoubleWord);
   }
+  void andw_(Register rd, Register rn, Operand o) {
+    EmitLogicalShiftOp(AND, rd, rn, o, kWord);
+  }
   void bic(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(BIC, rd, rn, o, kDoubleWord);
   }
   void orr(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(ORR, rd, rn, o, kDoubleWord);
   }
   void orn(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(ORN, rd, rn, o, kDoubleWord);
   }
   void eor(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(EOR, rd, rn, o, kDoubleWord);
   }
+  void eorw(Register rd, Register rn, Operand o) {
+    EmitLogicalShiftOp(EOR, rd, rn, o, kWord);
+  }
   void eon(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(EON, rd, rn, o, kDoubleWord);
   }
   void ands(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(ANDS, rd, rn, o, kDoubleWord);
   }
   void bics(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(BICS, rd, rn, o, kDoubleWord);
   }
 
@@ skipping 275 matching lines @@
   void tst(Register rn, Operand o) {
     ands(ZR, rn, o);
   }
   void tsti(Register rn, uint64_t imm) {
     andis(ZR, rn, imm);
   }
 
   void Lsl(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, LSL, shift));
   }
+  void Lslw(Register rd, Register rn, int shift) {
+    addw(rd, ZR, Operand(rn, LSL, shift));
+  }
   void Lsr(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, LSR, shift));
   }
+  void Lsrw(Register rd, Register rn, int shift) {
+    addw(rd, ZR, Operand(rn, LSR, shift));

[regis, 2014/05/19 20:14:02]

Is a shift amount > 31 allowed? Are all 64 bits of rn taken into consideration?

[zra, 2014/05/19 21:13:18]

Ah, no. A shift > 31 is not allowed. I've added an ASSERT. Instructions in
32-bit mode only operate on the bottom 32 bits, so this instruction will shift
in zeros.

+  }
   void Asr(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, ASR, shift));
   }
 
   void SmiUntag(Register reg) {
     Asr(reg, reg, kSmiTagSize);
   }
   void SmiTag(Register reg) {
     Lsl(reg, reg, kSmiTagSize);
   }
@@ skipping 603 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_