MIPS[64]: Support for some SIMD operations (2)

MIPS[64]: Support for some SIMD operations (2)

Add support for F32x4Splat, F32x4ExtractLane,
F32x4ReplaceLane, F32x4SConvertI32x4, F32x4UConvertI32x4
operations for mips32 and mips64 architectures.

BUG=

Note: Depends on https://codereview.chromium.org/2753903004/
Review-Url: https://codereview.chromium.org/2780503002
Cr-Commit-Position: refs/heads/master@{#44359}
Committed: https://chromium.googlesource.com/v8/v8/+/5606d50ff69cc508e469c1b6f45223e99bdf6908

[dusan.simicic, 2017-03-27 14:25:34]

dusan.simicic@imgtec.com changed reviewers:
+ bbudge@chromium.org, ivica.bogosavljevic@imgtec.com, titzer@chromium.org,
v8-mips-ports@googlegroups.com

[dusan.simicic, 2017-03-27 14:25:34]

PTAL

[bbudge, 2017-03-27 17:18:25]

lgtm

I think MIPS 32 bit floating point registers combine to form larger registers.
If floats combine to form doubles, and double to form simd vectors, then you
should probably switch the register allocator to the more complex aliasing kind:

https://cs.chromium.org/chromium/src/v8/src/mips/assembler-mips.h?rcl=f4848b5...

Should be false.

[dusan.simicic, 2017-03-28 09:48:19]

On 2017/03/27 17:18:25, bbudge wrote:
> lgtm
> 
> I think MIPS 32 bit floating point registers combine to form larger registers.
> If floats combine to form doubles, and double to form simd vectors, then you
> should probably switch the register allocator to the more complex aliasing
kind:
> 
>
https://cs.chromium.org/chromium/src/v8/src/mips/assembler-mips.h?rcl=f4848b5...
> 
> Should be false.

Two 32bit floating point registers are combined to form one 64bit double
register only on system with 32bit FP unit (FR=0 mode). When we have 64bit FPU
(FR=1 mode) all 32 registers can be used as single or double. MSA extension
requires FR=1 mode (64bit FP unit) and 32 SIMD registers are mapped to FP
registers (single FP reg is mapped to lower 32bits of MSA reg, and double FP reg
is mapped to lower 64bits of MSA reg). I think this match with SimpleFPAliasing
scheme, only drawback is that we are using only even FP registers in order to
maintain compatibility with FR=0 mode, so only subset of SIMD registers will be
allocatable.

[bbudge, 2017-03-28 15:39:37]

On 2017/03/28 09:48:19, dusan.simicic wrote:
> On 2017/03/27 17:18:25, bbudge wrote:
> > lgtm
> > 
> > I think MIPS 32 bit floating point registers combine to form larger
registers.
> > If floats combine to form doubles, and double to form simd vectors, then you
> > should probably switch the register allocator to the more complex aliasing
> kind:
> > 
> >
>
https://cs.chromium.org/chromium/src/v8/src/mips/assembler-mips.h?rcl=f4848b5...
> > 
> > Should be false.
> 
> Two 32bit floating point registers are combined to form one 64bit double
> register only on system with 32bit FP unit (FR=0 mode). When we have 64bit FPU
> (FR=1 mode) all 32 registers can be used as single or double. MSA extension
> requires FR=1 mode (64bit FP unit) and 32 SIMD registers are mapped to FP
> registers (single FP reg is mapped to lower 32bits of MSA reg, and double FP
reg
> is mapped to lower 64bits of MSA reg). I think this match with
SimpleFPAliasing
> scheme, only drawback is that we are using only even FP registers in order to
> maintain compatibility with FR=0 mode, so only subset of SIMD registers will
be
> allocatable.

OK, thanks for the explanation.

[dusan.simicic, 2017-04-03 09:21:19]

Description was changed from

==========
MIPS[64]: Support for some SIMD operations (2)

Add support for Float32x4Splat, Float32x4ExtractLane,
Float32x4ReplaceLane, Float32x4FromInt32x4, Float32x4FromUint32x4
operations for mips32 and mips64 architectures.

BUG=

Note: Depends on https://codereview.chromium.org/2753903004/
==========

to

==========
MIPS[64]: Support for some SIMD operations (2)

Add support for F32x4Splat, F32x4ExtractLane,
F32x4ReplaceLane, F32x4SConvertI32x4, F32x4UConvertI32x4
operations for mips32 and mips64 architectures.

BUG=

Note: Depends on https://codereview.chromium.org/2753903004/
==========

[dusan.simicic, 2017-04-03 09:23:41]

dusan.simicic@imgtec.com changed reviewers:
+ mtrofin@chromium.org

[dusan.simicic, 2017-04-03 09:23:42]

PS2: rebased and changed opcode names according to
https://codereview.chromium.org/2776753004/

+ mtrofin for instruction-selector.cc

[Mircea Trofin, 2017-04-03 13:44:30]

On 2017/04/03 09:23:42, dusan.simicic wrote:
> PS2: rebased and changed opcode names according to
> https://codereview.chromium.org/2776753004/
> 
> + mtrofin for instruction-selector.cc

Lgtm

[dusan.simicic, 2017-04-03 13:56:42]

The CQ bit was checked by dusan.simicic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2017-04-03 13:56:54]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-03 14:20:18]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-04-03 14:20:19]

Dry run: This issue passed the CQ dry run.

[dusan.simicic, 2017-04-04 07:01:32]

The CQ bit was checked by dusan.simicic@imgtec.com

[dusan.simicic, 2017-04-04 07:01:33]

The patchset sent to the CQ was uploaded after l-g-t-m from bbudge@chromium.org
Link to the patchset: https://codereview.chromium.org/2780503002/#ps20001
(title: "rebased")

[commit-bot: I haz the power, 2017-04-04 07:01:40]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-04-04 07:03:07]

CQ is committing da patch.

Bot data: {"patchset_id": 20001, "attempt_start_ts": 1491289292619600,
"parent_rev": "7c10795209f7ec6d0da717416e42c79bc228d27a", "commit_rev":
"5606d50ff69cc508e469c1b6f45223e99bdf6908"}

[commit-bot: I haz the power, 2017-04-04 07:03:12]

Description was changed from

==========
MIPS[64]: Support for some SIMD operations (2)

Add support for F32x4Splat, F32x4ExtractLane,
F32x4ReplaceLane, F32x4SConvertI32x4, F32x4UConvertI32x4
operations for mips32 and mips64 architectures.

BUG=

Note: Depends on https://codereview.chromium.org/2753903004/
==========

to

==========
MIPS[64]: Support for some SIMD operations (2)

Add support for F32x4Splat, F32x4ExtractLane,
F32x4ReplaceLane, F32x4SConvertI32x4, F32x4UConvertI32x4
operations for mips32 and mips64 architectures.

BUG=

Note: Depends on https://codereview.chromium.org/2753903004/
Review-Url: https://codereview.chromium.org/2780503002
Cr-Commit-Position: refs/heads/master@{#44359}
Committed:
https://chromium.googlesource.com/v8/v8/+/5606d50ff69cc508e469c1b6f45223e99bd...
==========

[commit-bot: I haz the power, 2017-04-04 07:03:13]

Committed patchset #2 (id:20001) as
https://chromium.googlesource.com/v8/v8/+/5606d50ff69cc508e469c1b6f45223e99bd...