Index: src/compiler/mips64/code-generator-mips64.cc |
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc |
index e06e165b5b0a7e6c78da0a6340b29b57a878a967..53d7a6439e8aa9503f1a06670427f1ee2e5b37c4 100644 |
--- a/src/compiler/mips64/code-generator-mips64.cc |
+++ b/src/compiler/mips64/code-generator-mips64.cc |
@@ -1971,6 +1971,39 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( |
i.InputSimd128Register(1)); |
break; |
} |
+ case kMips64F32x4Splat: { |
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD); |
+ __ FmoveLow(kScratchReg, i.InputSingleRegister(0)); |
+ __ fill_w(i.OutputSimd128Register(), kScratchReg); |
+ break; |
+ } |
+ case kMips64F32x4ExtractLane: { |
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD); |
+ __ copy_u_w(kScratchReg, i.InputSimd128Register(0), i.InputInt8(1)); |
+ __ FmoveLow(i.OutputSingleRegister(), kScratchReg); |
+ break; |
+ } |
+ case kMips64F32x4ReplaceLane: { |
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD); |
+ Simd128Register src = i.InputSimd128Register(0); |
+ Simd128Register dst = i.OutputSimd128Register(); |
+ if (!src.is(dst)) { |
+ __ move_v(dst, src); |
+ } |
+ __ FmoveLow(kScratchReg, i.InputSingleRegister(2)); |
+ __ insert_w(dst, i.InputInt8(1), kScratchReg); |
+ break; |
+ } |
+ case kMips64F32x4SConvertI32x4: { |
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD); |
+ __ ffint_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0)); |
+ break; |
+ } |
+ case kMips64F32x4UConvertI32x4: { |
+ CpuFeatureScope msa_scope(masm(), MIPS_SIMD); |
+ __ ffint_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0)); |
+ break; |
+ } |
} |
return kSuccess; |
} // NOLINT(readability/fn_size) |